; Test basic code generation for i32 memory WebAssembly instructions. test compile ; We only test on 64-bit since the heap_addr instructions and vmctx parameters ; explicitly mention the pointer width. set is_64bit=1 isa intel haswell function %i32_load(i32, i64 vmctx) -> i32 { gv0 = vmctx heap0 = static gv0, min 0x0001_0000, bound 0x0001_0000_0000, guard 0x8000_0000 ebb0(v0: i32, v1: i64): v2 = heap_addr.i64 heap0, v0, 1 v3 = load.i32 v2 return v3 } function %i32_store(i32, i32, i64 vmctx) { gv0 = vmctx heap0 = static gv0, min 0x0001_0000, bound 0x0001_0000_0000, guard 0x8000_0000 ebb0(v0: i32, v1: i32, v2: i64): v3 = heap_addr.i64 heap0, v1, 1 store v0, v3 return } function %i32_load8_s(i32, i64 vmctx) -> i32 { gv0 = vmctx heap0 = static gv0, min 0x0001_0000, bound 0x0001_0000_0000, guard 0x8000_0000 ebb0(v0: i32, v1: i64): v2 = heap_addr.i64 heap0, v0, 1 v3 = sload8.i32 v2 return v3 } function %i32_load8_u(i32, i64 vmctx) -> i32 { gv0 = vmctx heap0 = static gv0, min 0x0001_0000, bound 0x0001_0000_0000, guard 0x8000_0000 ebb0(v0: i32, v1: i64): v2 = heap_addr.i64 heap0, v0, 1 v3 = uload8.i32 v2 return v3 } function %i32_store8(i32, i32, i64 vmctx) { gv0 = vmctx heap0 = static gv0, min 0x0001_0000, bound 0x0001_0000_0000, guard 0x8000_0000 ebb0(v0: i32, v1: i32, v2: i64): v3 = heap_addr.i64 heap0, v1, 1 istore8 v0, v3 return } function %i32_load16_s(i32, i64 vmctx) -> i32 { gv0 = vmctx heap0 = static gv0, min 0x0001_0000, bound 0x0001_0000_0000, guard 0x8000_0000 ebb0(v0: i32, v1: i64): v2 = heap_addr.i64 heap0, v0, 1 v3 = sload16.i32 v2 return v3 } function %i32_load16_u(i32, i64 vmctx) -> i32 { gv0 = vmctx heap0 = static gv0, min 0x0001_0000, bound 0x0001_0000_0000, guard 0x8000_0000 ebb0(v0: i32, v1: i64): v2 = heap_addr.i64 heap0, v0, 1 v3 = uload16.i32 v2 return v3 } function %i32_store16(i32, i32, i64 vmctx) { gv0 = vmctx heap0 = static gv0, min 0x0001_0000, bound 0x0001_0000_0000, guard 0x8000_0000 ebb0(v0: i32, v1: i32, v2: i64): v3 = heap_addr.i64 heap0, v1, 1 istore16 v0, v3 return }