better vcode printing

Cargo.lock

@@ -607,7 +607,7 @@ dependencies = [
  "cranelift-isle",
  "criterion",
  "gimli",
- "hashbrown 0.13.1",
+ "hashbrown 0.13.2",
  "log",
  "regalloc2",
  "serde",
@@ -677,7 +677,7 @@ name = "cranelift-frontend"
 version = "0.96.0"
 dependencies = [
  "cranelift-codegen",
- "hashbrown 0.13.1",
+ "hashbrown 0.13.2",
  "log",
  "similar",
  "smallvec",
@@ -747,7 +747,7 @@ dependencies = [
  "anyhow",
  "cranelift-codegen",
  "cranelift-control",
- "hashbrown 0.13.1",
+ "hashbrown 0.13.2",
 ]
 
 [[package]]
@@ -837,7 +837,7 @@ dependencies = [
  "cranelift-codegen",
  "cranelift-entity",
  "cranelift-frontend",
- "hashbrown 0.13.1",
+ "hashbrown 0.13.2",
  "itertools",
  "log",
  "serde",
@@ -1498,9 +1498,9 @@ checksum = "8a9ee70c43aaf417c914396645a0fa852624801b24ebb7ae78fe8272889ac888"
 
 [[package]]
 name = "hashbrown"
-version = "0.13.1"
+version = "0.13.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "33ff8ae62cd3a9102e5637afc8452c55acf3844001bd5374e0b0bd7b6616c038"
+checksum = "43a3c133739dddd0d2990f9a4bdf8eb4b21ef50e4851ca85ab661199821d510e"
 dependencies = [
  "ahash",
 ]
@@ -2049,7 +2049,7 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "ea86265d3d3dcb6a27fc51bd29a4bf387fae9d2986b823079d4986af253eb439"
 dependencies = [
  "crc32fast",
- "hashbrown 0.13.1",
+ "hashbrown 0.13.2",
  "indexmap",
  "memchr",
 ]
@@ -2578,11 +2578,10 @@ dependencies = [
 [[package]]
 name = "regalloc2"
 version = "0.6.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "80535183cae11b149d618fbd3c37e38d7cda589d82d7769e196ca9a9042d7621"
 dependencies = [
- "fxhash",
+ "hashbrown 0.13.2",
  "log",
+ "rustc-hash",
  "serde",
  "slice-group-by",
  "smallvec",
@@ -2674,6 +2673,12 @@ version = "0.1.21"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "7ef03e0a2b150c7a90d01faf6254c9c48a41e95fb2a8c2ac1c6f0d2b9aefc342"
 
+[[package]]
+name = "rustc-hash"
+version = "1.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "08d43f7aa6b08d49f382cde6a7982047c3426db949b1424bc4b7ec9ae12c6ce2"
+
 [[package]]
 name = "rustix"
 version = "0.36.8"

Cargo.toml

@@ -84,6 +84,9 @@ anyhow = { workspace = true }
 [profile.release.build-override]
 opt-level = 0
 
+[profile.release]
+debug = true
+
 [workspace]
 resolver = '2'
 members = [

cranelift/codegen/Cargo.toml

@@ -27,7 +27,7 @@ serde = { version = "1.0.94", features = ["derive"], optional = true }
 bincode = { version = "1.2.1", optional = true }
 gimli = { workspace = true, features = ["write"], optional = true }
 smallvec = { workspace = true }
-regalloc2 = { version = "0.6.1", features = ["checker"] }
+regalloc2 = { path = "../../../regalloc2/", features = ["checker", "trace-log"] }
 souper-ir = { version = "2.1.0", optional = true }
 sha2 = { version = "0.10.2", optional = true }
 # It is a goal of the cranelift-codegen crate to have minimal external dependencies.

cranelift/codegen/src/isa/aarch64/inst/regs.rs

@@ -230,6 +230,7 @@ pub fn create_reg_env(flags: &settings::Flags) -> MachineEnv {
             ],
         ],
         fixed_stack_slots: vec![],
+        scratch_by_class: [None, None],
     };
 
     if !flags.enable_pinned_reg() {

cranelift/codegen/src/isa/riscv64/inst/regs.rs

@@ -182,6 +182,7 @@ pub fn crate_reg_eviroment(_flags: &settings::Flags) -> MachineEnv {
         preferred_regs_by_class,
         non_preferred_regs_by_class,
         fixed_stack_slots: vec![],
+        scratch_by_class: [None, None],
     }
 }
 

cranelift/codegen/src/isa/s390x/inst/regs.rs

@@ -151,6 +151,7 @@ pub fn create_machine_env(_flags: &settings::Flags) -> MachineEnv {
             ],
         ],
         fixed_stack_slots: vec![],
+        scratch_by_class: [None, None],
     }
 }
 

cranelift/codegen/src/isa/x64/inst/regs.rs

@@ -203,6 +203,7 @@ pub(crate) fn create_reg_env_systemv(flags: &settings::Flags) -> MachineEnv {
             vec![],
         ],
         fixed_stack_slots: vec![],
+        scratch_by_class: [None, None]
     };
 
     debug_assert_eq!(r15(), pinned_reg());

cranelift/codegen/src/machinst/compile.rs

@@ -51,6 +51,7 @@ pub fn compile<B: LowerBackend + TargetIsa>(
         let _tt = timing::regalloc();
         let mut options = RegallocOptions::default();
         options.verbose_log = b.flags().regalloc_verbose_logs();
+        options.fast_alloc = true;
 
         if cfg!(debug_assertions) {
             options.validate_ssa = true;

cranelift/codegen/src/machinst/vcode.rs

@@ -771,6 +771,7 @@ impl<I: VCodeInst> VCode<I> {
     {
         // To write into disasm string.
         use core::fmt::Write;
+        let want_disasm = true;
 
         let _tt = timing::vcode_emit();
         let mut buffer = MachBuffer::new();
@@ -908,6 +909,7 @@ impl<I: VCodeInst> VCode<I> {
             for inst_or_edit in regalloc.block_insts_and_edits(&self, block) {
                 match inst_or_edit {
                     InstOrEdit::Inst(iix) => {
+                        trace!("Emitting inst {}", iix.index());
                         if !self.debug_value_labels.is_empty() {
                             // If we need to produce debug info,
                             // record the offset of each instruction
@@ -933,7 +935,7 @@ impl<I: VCodeInst> VCode<I> {
                             // and they come out the other end, if
                             // still needed (not elided), as
                             // regalloc-inserted moves.
-                            continue;
+                            //continue;
                         }
 
                         // Update the srcloc at this point in the buffer.
@@ -1009,6 +1011,7 @@ impl<I: VCodeInst> VCode<I> {
                         // immediately emit it.
                         match (from.as_reg(), to.as_reg()) {
                             (Some(from), Some(to)) => {
+                                trace!("Emitting move from {} to {}", from, to);
                                 // Reg-to-reg move.
                                 let from_rreg = Reg::from(from);
                                 let to_rreg = Writable::from_reg(Reg::from(to));
@@ -1018,6 +1021,7 @@ impl<I: VCodeInst> VCode<I> {
                                 do_emit(&mv, &[], &mut disasm, &mut buffer, &mut state);
                             }
                             (Some(from), None) => {
+                                trace!("Emitting move from {} to slot {}", from, to.as_stack().unwrap().index());
                                 // Spill from register to spillslot.
                                 let to = to.as_stack().unwrap();
                                 let from_rreg = RealReg::from(from);
@@ -1025,6 +1029,7 @@ impl<I: VCodeInst> VCode<I> {
                                 do_emit(&spill, &[], &mut disasm, &mut buffer, &mut state);
                             }
                             (None, Some(to)) => {
+                                trace!("Emitting move from slot {} to {}", from.as_stack().unwrap().index(), to);
                                 // Load from spillslot to register.
                                 let from = from.as_stack().unwrap();
                                 let to_rreg = Writable::from_reg(RealReg::from(to));
@@ -1100,6 +1105,10 @@ impl<I: VCodeInst> VCode<I> {
             self.compute_value_labels_ranges(regalloc, &inst_offsets[..], func_body_len);
         let frame_size = self.abi.frame_size();
 
+        if want_disasm {
+            trace!("Disassembly:\n{}", disasm);
+        }
+
         EmitResult {
             buffer,
             bb_offsets,
@@ -1282,14 +1291,6 @@ impl<I: VCodeInst> RegallocFunction for VCode<I> {
         self.insts[insn.index()].is_safepoint()
     }
 
-    fn is_move(&self, insn: InsnIndex) -> Option<(Operand, Operand)> {
-        let (a, b) = self.is_move.get(&insn)?;
-        Some((
-            self.assert_operand_not_vreg_alias(*a),
-            self.assert_operand_not_vreg_alias(*b),
-        ))
-    }
-
     fn inst_operands(&self, insn: InsnIndex) -> &[Operand] {
         let (start, end) = self.operand_ranges[insn.index()];
         let ret = &self.operands[start as usize..end as usize];
@@ -1349,12 +1350,39 @@ impl<I: VCodeInst> fmt::Debug for VCode<I> {
 
         for block in 0..self.num_blocks() {
             let block = BlockIndex::new(block);
-            writeln!(f, "Block {}:", block.index())?;
+            write!(f, "Block {}(", block.index())?;
+            {
+                let mut first = true;
+                for vreg in self.block_params(block) {
+                    if !first {
+                        write!(f, ", ")?;
+                    } else {
+                        first = false;
+                    }
+                    write!(f, "{}", vreg)?;
+                }
+            }
+            writeln!(f, "):")?;
             if let Some(bb) = self.bindex_to_bb(block) {
                 writeln!(f, "    (original IR block: {})", bb)?;
             }
-            for succ in self.succs(block) {
+            for (i, succ) in self.succs(block).iter().enumerate() {
-                writeln!(f, "    (successor: Block {})", succ.index())?;
+                let last_inst = self.block_insns(block).last();
+                if self.is_branch(last_inst) {
+                    write!(f, "    (successor: Block {}(", succ.index())?;
+                    let mut first = true;
+                    for vreg in self.branch_blockparams(block, last_inst, i) {
+                        if !first {
+                            write!(f, ", ")?;
+                        } else {
+                            first = false;
+                        }
+                        write!(f, "{}", vreg)?;
+                    }
+                    writeln!(f, "))")?;
+                } else {
+                    write!(f, "    (successor: Block {})", succ.index())?;
+                }
             }
             let (start, end) = self.block_ranges[block.index()];
             writeln!(

cranelift/filetests/src/function_runner.rs

@@ -17,6 +17,7 @@ use std::cmp::max;
 use std::collections::hash_map::Entry;
 use std::collections::HashMap;
 use thiserror::Error;
+use log::trace;
 
 const TESTFILE_NAMESPACE: u32 = 0;
 
@@ -191,6 +192,7 @@ impl TestFileCompiler {
         // First, rename the function
         let func_original_name = func.name;
         func.name = UserFuncName::User(defined_func.new_name.clone());
+        trace!("Rename func from '{}' to '{}'", func_original_name, func.name);
 
         // Rename any functions that it references
         // Do this in stages to appease the borrow checker
@@ -233,6 +235,10 @@ impl TestFileCompiler {
             .get(&func.name)
             .ok_or(anyhow!("Undeclared function {} found!", &func.name))?;
 
+        if log::log_enabled!(log::Level::Trace) {
+            self.ctx.set_disasm(true);
+        }
+
         self.ctx.func = self.apply_func_rename(func, defined_func)?;
         self.module.define_function_with_control_plane(
             defined_func.func_id,
@@ -277,6 +283,11 @@ impl TestFileCompiler {
         // available).
         self.module.finalize_definitions()?;
 
+        for (name, func) in self.defined_functions.iter() {
+            let ptr = self.module.get_finalized_function(func.func_id);
+            trace!("Function '{}' at {:#X}", name, ptr as u64);
+        }
+
         Ok(CompiledTestFile {
             module: Some(self.module),
             defined_functions: self.defined_functions,

winch/codegen/Cargo.toml

@@ -17,7 +17,7 @@ target-lexicon = { workspace = true, features = ["std"] }
 # In the next iteration we'll factor out the common bits so that they can be consumed
 # by Cranelift and Winch.
 cranelift-codegen = { workspace = true }
-regalloc2 = "0.6.0"
+regalloc2 = { path = "../../../regalloc2" }
 gimli = { workspace = true }
 
 [features]