changes

`FunctionBuilder::create_stackslot` was split into `create_sized_stack_slot`
and `create_dynamic_stack_slot`. This updates the doc in the `StackBuilder`
docstring to refer to the new methods.

Fixes #5838.

.github/workflows/main.yml

@@ -478,7 +478,7 @@ jobs:
           submodules: true
       - uses: ./.github/actions/install-rust
       - run: rustup target add wasm32-wasi
-      - uses: abrown/install-openvino-action@50a2ab733ef4b504dd7de3ac45c36eae7f9bc228
+      - uses: abrown/install-openvino-action@v6
         with:
           version: 2022.3.0
           apt: true

cranelift/codegen/meta/src/shared/instructions.rs

@@ -2415,7 +2415,7 @@ pub(crate) fn define(
         places, shifting in zero bits to the MSB. Also called a *logical
         shift*.
 
-        The shift amount is masked to the size of the register.
+        The shift amount is masked to the size of ``x``.
 
         When shifting a B-bits integer type, this instruction computes:
 
@@ -2441,7 +2441,7 @@ pub(crate) fn define(
         places, shifting in sign bits to the MSB. Also called an *arithmetic
         shift*.
 
-        The shift amount is masked to the size of the register.
+        The shift amount is masked to the size of ``x``.
         "#,
             &formats.binary,
         )
@@ -2475,7 +2475,7 @@ pub(crate) fn define(
             r#"
         Unsigned shift right by immediate.
 
-        The shift amount is masked to the size of the register.
+        The shift amount is masked to the size of ``x``.
         "#,
             &formats.binary_imm64,
         )
@@ -2492,7 +2492,7 @@ pub(crate) fn define(
             r#"
         Signed shift right by immediate.
 
-        The shift amount is masked to the size of the register.
+        The shift amount is masked to the size of ``x``.
         "#,
             &formats.binary_imm64,
         )

cranelift/codegen/meta/src/shared/settings.rs

@@ -53,19 +53,6 @@ pub(crate) fn define() -> SettingGroup {
         true,
     );
 
-    settings.add_bool(
-        "use_egraphs",
-        "Enable egraph-based optimization.",
-        r#"
-            This enables an optimization phase that converts CLIF to an egraph (equivalence graph)
-            representation, performs various rewrites, and then converts it back. This should result in
-            better optimization, but the traditional optimization pass structure is also still
-            available by setting this to `false`. The `false` setting will eventually be
-            deprecated and removed.
-        "#,
-        true,
-    );
-
     settings.add_bool(
         "enable_verifier",
         "Run the Cranelift IR verifier at strategic times during compilation.",

cranelift/codegen/src/context.rs

@@ -17,15 +17,12 @@ use crate::flowgraph::ControlFlowGraph;
 use crate::ir::Function;
 use crate::isa::TargetIsa;
 use crate::legalizer::simple_legalize;
-use crate::licm::do_licm;
 use crate::loop_analysis::LoopAnalysis;
 use crate::machinst::{CompiledCode, CompiledCodeStencil};
 use crate::nan_canonicalization::do_nan_canonicalization;
 use crate::remove_constant_phis::do_remove_constant_phis;
 use crate::result::{CodegenResult, CompileResult};
 use crate::settings::{FlagsOrIsa, OptLevel};
-use crate::simple_gvn::do_simple_gvn;
-use crate::simple_preopt::do_preopt;
 use crate::trace;
 use crate::unreachable_code::eliminate_unreachable_code;
 use crate::verifier::{verify_context, VerifierErrors, VerifierResult};
@@ -172,22 +169,12 @@ impl Context {
         );
 
         self.compute_cfg();
-        if !isa.flags().use_egraphs() && opt_level != OptLevel::None {
-            self.preopt(isa)?;
-        }
         if isa.flags().enable_nan_canonicalization() {
             self.canonicalize_nans(isa)?;
         }
 
         self.legalize(isa)?;
 
-        if !isa.flags().use_egraphs() && opt_level != OptLevel::None {
-            self.compute_domtree();
-            self.compute_loop_analysis();
-            self.licm(isa)?;
-            self.simple_gvn(isa)?;
-        }
-
         self.compute_domtree();
         self.eliminate_unreachable_code(isa)?;
 
@@ -198,14 +185,7 @@ impl Context {
         self.remove_constant_phis(isa)?;
 
         if opt_level != OptLevel::None {
-            if isa.flags().use_egraphs() {
+            self.egraph_pass()?;
-                self.egraph_pass()?;
-            } else if isa.flags().enable_alias_analysis() {
-                for _ in 0..2 {
-                    self.replace_redundant_loads()?;
-                    self.simple_gvn(isa)?;
-                }
-            }
         }
 
         Ok(())
@@ -294,13 +274,6 @@ impl Context {
         Ok(())
     }
 
-    /// Perform pre-legalization rewrites on the function.
-    pub fn preopt(&mut self, isa: &dyn TargetIsa) -> CodegenResult<()> {
-        do_preopt(&mut self.func, isa);
-        self.verify_if(isa)?;
-        Ok(())
-    }
-
     /// Perform NaN canonicalizing rewrites on the function.
     pub fn canonicalize_nans(&mut self, isa: &dyn TargetIsa) -> CodegenResult<()> {
         do_nan_canonicalization(&mut self.func);
@@ -341,23 +314,6 @@ impl Context {
         self.compute_domtree()
     }
 
-    /// Perform simple GVN on the function.
-    pub fn simple_gvn<'a, FOI: Into<FlagsOrIsa<'a>>>(&mut self, fisa: FOI) -> CodegenResult<()> {
-        do_simple_gvn(&mut self.func, &mut self.domtree);
-        self.verify_if(fisa)
-    }
-
-    /// Perform LICM on the function.
-    pub fn licm(&mut self, isa: &dyn TargetIsa) -> CodegenResult<()> {
-        do_licm(
-            &mut self.func,
-            &mut self.cfg,
-            &mut self.domtree,
-            &mut self.loop_analysis,
-        );
-        self.verify_if(isa)
-    }
-
     /// Perform unreachable code elimination.
     pub fn eliminate_unreachable_code<'a, FOI>(&mut self, fisa: FOI) -> CodegenResult<()>
     where

cranelift/codegen/src/fx.rs

@@ -23,11 +23,6 @@ pub fn FxHashMap<K: Hash + Eq, V>() -> FxHashMap<K, V> {
     HashMap::default()
 }
 
-#[allow(non_snake_case)]
-pub fn FxHashSet<V: Hash + Eq>() -> FxHashSet<V> {
-    HashSet::default()
-}
-
 /// A speedy hash algorithm for use within rustc. The hashmap in liballoc
 /// by default uses SipHash which isn't quite as speedy as we want. In the
 /// compiler we're not really worried about DOS attempts, so we use a fast

cranelift/codegen/src/ir/entities.rs

@@ -106,7 +106,9 @@ entity_impl!(Inst, "inst");
 /// [call stack](https://en.wikipedia.org/wiki/Call_stack).
 ///
 /// `StackSlot`s can be created with
-/// [`FunctionBuilder::create_stackslot`](https://docs.rs/cranelift-frontend/*/cranelift_frontend/struct.FunctionBuilder.html#method.create_stack_slot).
+/// [`FunctionBuilder::create_sized_stack_slot`](https://docs.rs/cranelift-frontend/*/cranelift_frontend/struct.FunctionBuilder.html#method.create_sized_stack_slot)
+/// or
+/// [`FunctionBuilder::create_dynamic_stack_slot`](https://docs.rs/cranelift-frontend/*/cranelift_frontend/struct.FunctionBuilder.html#method.create_dynamic_stack_slot).
 ///
 /// `StackSlot`s are most often used with
 /// [`stack_addr`](super::InstBuilder::stack_addr),

cranelift/codegen/src/ir/instructions.rs

@@ -933,6 +933,7 @@ mod tests {
         assert!(cmp.requires_typevar_operand());
         assert_eq!(cmp.num_fixed_results(), 1);
         assert_eq!(cmp.num_fixed_value_arguments(), 2);
+        assert_eq!(cmp.result_type(0, types::I64), types::I8);
     }
 
     #[test]

cranelift/codegen/src/lib.rs

@@ -102,21 +102,17 @@ mod constant_hash;
 mod context;
 mod ctxhash;
 mod dce;
-mod divconst_magic_numbers;
 mod egraph;
 mod fx;
 mod inst_predicates;
 mod isle_prelude;
 mod iterators;
 mod legalizer;
-mod licm;
 mod nan_canonicalization;
 mod opts;
 mod remove_constant_phis;
 mod result;
 mod scoped_hash_map;
-mod simple_gvn;
-mod simple_preopt;
 mod unionfind;
 mod unreachable_code;
 mod value_label;

cranelift/codegen/src/licm.rs

@@ -1,241 +0,0 @@
-//! A Loop Invariant Code Motion optimization pass
-
-use crate::cursor::{Cursor, FuncCursor};
-use crate::dominator_tree::DominatorTree;
-use crate::entity::{EntityList, ListPool};
-use crate::flowgraph::{BlockPredecessor, ControlFlowGraph};
-use crate::fx::FxHashSet;
-use crate::ir::{
-    Block, DataFlowGraph, Function, Inst, InstBuilder, InstructionData, Layout, Opcode, Type, Value,
-};
-use crate::loop_analysis::{Loop, LoopAnalysis};
-use crate::timing;
-use alloc::vec::Vec;
-
-/// Performs the LICM pass by detecting loops within the CFG and moving
-/// loop-invariant instructions out of them.
-/// Changes the CFG and domtree in-place during the operation.
-pub fn do_licm(
-    func: &mut Function,
-    cfg: &mut ControlFlowGraph,
-    domtree: &mut DominatorTree,
-    loop_analysis: &mut LoopAnalysis,
-) {
-    let _tt = timing::licm();
-    debug_assert!(cfg.is_valid());
-    debug_assert!(domtree.is_valid());
-    debug_assert!(loop_analysis.is_valid());
-
-    for lp in loop_analysis.loops() {
-        // For each loop that we want to optimize we determine the set of loop-invariant
-        // instructions
-        let invariant_insts = remove_loop_invariant_instructions(lp, func, cfg, loop_analysis);
-        // Then we create the loop's pre-header and fill it with the invariant instructions
-        // Then we remove the invariant instructions from the loop body
-        if !invariant_insts.is_empty() {
-            // If the loop has a natural pre-header we use it, otherwise we create it.
-            let mut pos;
-            match has_pre_header(&func.layout, cfg, domtree, loop_analysis.loop_header(lp)) {
-                None => {
-                    let pre_header =
-                        create_pre_header(loop_analysis.loop_header(lp), func, cfg, domtree);
-                    pos = FuncCursor::new(func).at_last_inst(pre_header);
-                }
-                // If there is a natural pre-header we insert new instructions just before the
-                // related jumping instruction (which is not necessarily at the end).
-                Some((_, last_inst)) => {
-                    pos = FuncCursor::new(func).at_inst(last_inst);
-                }
-            };
-            // The last instruction of the pre-header is the termination instruction (usually
-            // a jump) so we need to insert just before this.
-            for inst in invariant_insts {
-                pos.insert_inst(inst);
-            }
-        }
-    }
-    // We have to recompute the domtree to account for the changes
-    cfg.compute(func);
-    domtree.compute(func, cfg);
-}
-
-/// Insert a pre-header before the header, modifying the function layout and CFG to reflect it.
-/// A jump instruction to the header is placed at the end of the pre-header.
-fn create_pre_header(
-    header: Block,
-    func: &mut Function,
-    cfg: &mut ControlFlowGraph,
-    domtree: &DominatorTree,
-) -> Block {
-    let pool = &mut ListPool::<Value>::new();
-    let header_args_values = func.dfg.block_params(header).to_vec();
-    let header_args_types: Vec<Type> = header_args_values
-        .into_iter()
-        .map(|val| func.dfg.value_type(val))
-        .collect();
-    let pre_header = func.dfg.make_block();
-    let mut pre_header_args_value: EntityList<Value> = EntityList::new();
-    for typ in header_args_types {
-        pre_header_args_value.push(func.dfg.append_block_param(pre_header, typ), pool);
-    }
-
-    for BlockPredecessor {
-        inst: last_inst, ..
-    } in cfg.pred_iter(header)
-    {
-        // We only follow normal edges (not the back edges)
-        if !domtree.dominates(header, last_inst, &func.layout) {
-            func.rewrite_branch_destination(last_inst, header, pre_header);
-        }
-    }
-
-    // Inserts the pre-header at the right place in the layout.
-    let mut pos = FuncCursor::new(func).at_top(header);
-    pos.insert_block(pre_header);
-    pos.next_inst();
-    pos.ins().jump(header, pre_header_args_value.as_slice(pool));
-
-    pre_header
-}
-
-/// Detects if a loop header has a natural pre-header.
-///
-/// A loop header has a pre-header if there is only one predecessor that the header doesn't
-/// dominate.
-/// Returns the pre-header Block and the instruction jumping to the header.
-fn has_pre_header(
-    layout: &Layout,
-    cfg: &ControlFlowGraph,
-    domtree: &DominatorTree,
-    header: Block,
-) -> Option<(Block, Inst)> {
-    let mut result = None;
-    for BlockPredecessor {
-        block: pred_block,
-        inst: branch_inst,
-    } in cfg.pred_iter(header)
-    {
-        // We only count normal edges (not the back edges)
-        if !domtree.dominates(header, branch_inst, layout) {
-            if result.is_some() {
-                // We have already found one, there are more than one
-                return None;
-            }
-            if branch_inst != layout.last_inst(pred_block).unwrap()
-                || cfg.succ_iter(pred_block).nth(1).is_some()
-            {
-                // It's along a critical edge, so don't use it.
-                return None;
-            }
-            result = Some((pred_block, branch_inst));
-        }
-    }
-    result
-}
-
-/// Test whether the given opcode is unsafe to even consider for LICM.
-fn trivially_unsafe_for_licm(opcode: Opcode) -> bool {
-    opcode.can_store()
-        || opcode.is_call()
-        || opcode.is_branch()
-        || opcode.is_terminator()
-        || opcode.is_return()
-        || opcode.can_trap()
-        || opcode.other_side_effects()
-}
-
-fn is_unsafe_load(inst_data: &InstructionData) -> bool {
-    match *inst_data {
-        InstructionData::Load { flags, .. } => !flags.readonly() || !flags.notrap(),
-        _ => inst_data.opcode().can_load(),
-    }
-}
-
-/// Test whether the given instruction is loop-invariant.
-fn is_loop_invariant(inst: Inst, dfg: &DataFlowGraph, loop_values: &FxHashSet<Value>) -> bool {
-    if trivially_unsafe_for_licm(dfg.insts[inst].opcode()) {
-        return false;
-    }
-
-    if is_unsafe_load(&dfg.insts[inst]) {
-        return false;
-    }
-
-    for arg in dfg.inst_values(inst) {
-        let arg = dfg.resolve_aliases(arg);
-        if loop_values.contains(&arg) {
-            return false;
-        }
-    }
-    true
-}
-
-/// Traverses a loop in reverse post-order from a header block and identify loop-invariant
-/// instructions. These loop-invariant instructions are then removed from the code and returned
-/// (in reverse post-order) for later use.
-fn remove_loop_invariant_instructions(
-    lp: Loop,
-    func: &mut Function,
-    cfg: &ControlFlowGraph,
-    loop_analysis: &LoopAnalysis,
-) -> Vec<Inst> {
-    let mut loop_values: FxHashSet<Value> = FxHashSet();
-    let mut invariant_insts: Vec<Inst> = Vec::new();
-    let mut pos = FuncCursor::new(func);
-    // We traverse the loop block in reverse post-order.
-    for block in postorder_blocks_loop(loop_analysis, cfg, lp).iter().rev() {
-        // Arguments of the block are loop values
-        for val in pos.func.dfg.block_params(*block) {
-            loop_values.insert(*val);
-        }
-        pos.goto_top(*block);
-        #[cfg_attr(feature = "cargo-clippy", allow(clippy::block_in_if_condition_stmt))]
-        while let Some(inst) = pos.next_inst() {
-            if is_loop_invariant(inst, &pos.func.dfg, &loop_values) {
-                // If all the instruction's argument are defined outside the loop
-                // then this instruction is loop-invariant
-                invariant_insts.push(inst);
-                // We remove it from the loop
-                pos.remove_inst_and_step_back();
-            } else {
-                // If the instruction is not loop-invariant we push its results in the set of
-                // loop values
-                for out in pos.func.dfg.inst_results(inst) {
-                    loop_values.insert(*out);
-                }
-            }
-        }
-    }
-    invariant_insts
-}
-
-/// Return blocks from a loop in post-order, starting from an entry point in the block.
-fn postorder_blocks_loop(
-    loop_analysis: &LoopAnalysis,
-    cfg: &ControlFlowGraph,
-    lp: Loop,
-) -> Vec<Block> {
-    let mut grey = FxHashSet();
-    let mut black = FxHashSet();
-    let mut stack = vec![loop_analysis.loop_header(lp)];
-    let mut postorder = Vec::new();
-
-    while !stack.is_empty() {
-        let node = stack.pop().unwrap();
-        if !grey.contains(&node) {
-            // This is a white node. Mark it as gray.
-            grey.insert(node);
-            stack.push(node);
-            // Get any children we've never seen before.
-            for child in cfg.succ_iter(node) {
-                if loop_analysis.is_in_loop(child, lp) && !grey.contains(&child) {
-                    stack.push(child);
-                }
-            }
-        } else if !black.contains(&node) {
-            postorder.push(node);
-            black.insert(node);
-        }
-    }
-    postorder
-}

cranelift/codegen/src/machinst/blockorder.rs

@@ -81,15 +81,6 @@ pub struct BlockLoweringOrder {
     /// Ranges in `lowered_succ_indices` giving the successor lists for each lowered
     /// block. Indexed by lowering-order index (`BlockIndex`).
     lowered_succ_ranges: Vec<(Option<Inst>, std::ops::Range<usize>)>,
-    /// Cold blocks. These blocks are not reordered in the
-    /// `lowered_order` above; the lowered order must respect RPO
-    /// (uses after defs) in order for lowering to be
-    /// correct. Instead, this set is used to provide `is_cold()`,
-    /// which is used by VCode emission to sink the blocks at the last
-    /// moment (when we actually emit bytes into the MachBuffer).
-    cold_blocks: FxHashSet<BlockIndex>,
-    /// Lowered blocks that are indirect branch targets.
-    indirect_branch_targets: FxHashSet<BlockIndex>,
 }
 
 #[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
@@ -98,6 +89,15 @@ pub enum LoweredBlock {
     Orig {
         /// Original CLIF block.
         block: Block,
+        /// Cold block. These blocks are not reordered in the
+        /// `lowered_order` above; the lowered order must respect RPO
+        /// (uses after defs) in order for lowering to be
+        /// correct. Instead, this bool is used to provide `is_cold()`,
+        /// which is used by VCode emission to sink the blocks at the last
+        /// moment (when we actually emit bytes into the MachBuffer).
+        cold: bool,
+        /// Target of indirect branch
+        indirect_branch_target: bool,
     },
 
     /// Critical edge between two CLIF blocks.
@@ -112,6 +112,11 @@ pub enum LoweredBlock {
         /// indexing order as `inst_predicates::visit_block_succs`. This is used to distinguish
         /// multiple edges between the same CLIF blocks.
         succ_idx: u32,
+
+        /// See [LoweredBlock::orig]
+        cold: bool,
+        /// See [LoweredBlock::orig]
+        indirect_branch_target: bool,
     },
 }
 
@@ -119,7 +124,7 @@ impl LoweredBlock {
     /// Unwrap an `Orig` block.
     pub fn orig_block(&self) -> Option<Block> {
         match self {
-            &LoweredBlock::Orig { block } => Some(block),
+            &LoweredBlock::Orig { block, .. } => Some(block),
             &LoweredBlock::CriticalEdge { .. } => None,
         }
     }
@@ -141,6 +146,20 @@ impl LoweredBlock {
             &LoweredBlock::Orig { .. } => None,
         }
     }
+
+    pub fn is_cold(&self) -> bool {
+        match self {
+            &LoweredBlock::CriticalEdge { cold, .. } => cold,
+            &LoweredBlock::Orig { cold, .. } => cold
+        }
+    }
+
+    pub fn is_indirect_branch_target(&self) -> bool {
+        match self {
+            &LoweredBlock::CriticalEdge { indirect_branch_target, .. } => indirect_branch_target,
+            &LoweredBlock::Orig { indirect_branch_target, .. } => indirect_branch_target
+        }
+    }
 }
 
 impl BlockLoweringOrder {
@@ -165,7 +184,7 @@ impl BlockLoweringOrder {
             visit_block_succs(f, block, |_, succ, from_table| {
                 block_out_count[block] += 1;
                 block_in_count[succ] += 1;
-                block_succs.push(LoweredBlock::Orig { block: succ });
+                block_succs.push(LoweredBlock::Orig { block: succ, cold: f.layout.is_cold(succ), indirect_branch_target: false });
 
                 if from_table {
                     indirect_branch_target_clif_blocks.insert(succ);
@@ -192,7 +211,7 @@ impl BlockLoweringOrder {
         let mut lowered_order = Vec::new();
 
         for &block in domtree.cfg_postorder().iter().rev() {
-            let lb = LoweredBlock::Orig { block };
+            let lb = LoweredBlock::Orig { block, cold: f.layout.is_cold(block), indirect_branch_target: indirect_branch_target_clif_blocks.contains(&block) };
             let bindex = BlockIndex::new(lowered_order.len());
             lb_to_bindex.insert(lb.clone(), bindex);
             lowered_order.push(lb);
@@ -208,6 +227,10 @@ impl BlockLoweringOrder {
                             pred: block,
                             succ,
                             succ_idx: succ_ix as u32,
+                            // Edges inherit indirect branch and cold block metadata from their
+                            // successor.
+                            cold: f.layout.is_cold(succ),
+                            indirect_branch_target: indirect_branch_target_clif_blocks.contains(&succ)
                         };
                         let bindex = BlockIndex::new(lowered_order.len());
                         lb_to_bindex.insert(*lb, bindex);
@@ -221,8 +244,6 @@ impl BlockLoweringOrder {
         // during the creation of `lowering_order`, as we need `lb_to_bindex` to be fully populated
         // first.
         let mut lowered_succ_indices = Vec::new();
-        let mut cold_blocks = FxHashSet::default();
-        let mut indirect_branch_targets = FxHashSet::default();
         let lowered_succ_ranges =
             Vec::from_iter(lowered_order.iter().enumerate().map(|(ix, lb)| {
                 let bindex = BlockIndex::new(ix);
@@ -230,18 +251,24 @@ impl BlockLoweringOrder {
                 let opt_inst = match lb {
                     // Block successors are pulled directly over, as they'll have been mutated when
                     // determining the block order already.
-                    &LoweredBlock::Orig { block } => {
+                    &LoweredBlock::Orig { block, .. } => {
                         let range = block_succ_range[block].clone();
                         lowered_succ_indices
-                            .extend(block_succs[range].iter().map(|lb| lb_to_bindex[lb]));
+                            .extend(block_succs[range].iter().map(|lb| {
-
+                                match lb {
-                        if f.layout.is_cold(block) {
+                                    LoweredBlock::Orig { block, cold, .. } => {
-                            cold_blocks.insert(bindex);
+                                        match lb_to_bindex.get(&LoweredBlock::Orig { block: *block, cold: *cold, indirect_branch_target: indirect_branch_target_clif_blocks.contains(block) } ) {
-                        }
+                                            Some(idx) => *idx,
-
+                                            None => {
-                        if indirect_branch_target_clif_blocks.contains(&block) {
+                                                panic!("Trying to hashlookup {:?} in HashMap: {:?}", lb, lb_to_bindex);
-                            indirect_branch_targets.insert(bindex);
+                                            }
-                        }
+                                        }
+                                    },
+                                    LoweredBlock::CriticalEdge { .. } => {
+                                        lb_to_bindex[&lb]
+                                    }
+                                }
+                            }));
 
                         let last = f.layout.last_inst(block).unwrap();
                         let opcode = f.dfg.insts[last].opcode();
@@ -253,21 +280,10 @@ impl BlockLoweringOrder {
 
                     // Critical edges won't have successor information in block_succ_range, but
                     // they only have a single known successor to record anyway.
-                    &LoweredBlock::CriticalEdge { succ, .. } => {
+                    &LoweredBlock::CriticalEdge { succ, cold, indirect_branch_target, .. } => {
-                        let succ_index = lb_to_bindex[&LoweredBlock::Orig { block: succ }];
+                        let succ_index = lb_to_bindex[&LoweredBlock::Orig { block: succ, cold, indirect_branch_target }];
                         lowered_succ_indices.push(succ_index);
 
-                        // Edges inherit indirect branch and cold block metadata from their
-                        // successor.
-
-                        if f.layout.is_cold(succ) {
-                            cold_blocks.insert(bindex);
-                        }
-
-                        if indirect_branch_target_clif_blocks.contains(&succ) {
-                            indirect_branch_targets.insert(bindex);
-                        }
-
                         None
                     }
                 };
@@ -278,9 +294,7 @@ impl BlockLoweringOrder {
         let result = BlockLoweringOrder {
             lowered_order,
             lowered_succ_indices,
-            lowered_succ_ranges,
+            lowered_succ_ranges
-            cold_blocks,
-            indirect_branch_targets,
         };
 
         trace!("BlockLoweringOrder: {:#?}", result);
@@ -300,13 +314,13 @@ impl BlockLoweringOrder {
 
     /// Determine whether the given lowered-block index is cold.
     pub fn is_cold(&self, block: BlockIndex) -> bool {
-        self.cold_blocks.contains(&block)
+        self.lowered_order[block.index()].is_cold()
     }
 
     /// Determine whether the given lowered block index is an indirect branch
     /// target.
     pub fn is_indirect_branch_target(&self, block: BlockIndex) -> bool {
-        self.indirect_branch_targets.contains(&block)
+        self.lowered_order[block.index()].is_indirect_branch_target()
     }
 }
 

cranelift/codegen/src/machinst/isle.rs

@@ -128,29 +128,6 @@ macro_rules! isle_lower_prelude_methods {
 
         #[inline]
         fn put_in_regs(&mut self, val: Value) -> ValueRegs {
-            // If the value is a constant, then (re)materialize it at each
-            // use. This lowers register pressure. (Only do this if we are
-            // not using egraph-based compilation; the egraph framework
-            // more efficiently rematerializes constants where needed.)
-            if !(self.backend.flags().use_egraphs()
-                && self.backend.flags().opt_level() != OptLevel::None)
-            {
-                let inputs = self.lower_ctx.get_value_as_source_or_const(val);
-                if inputs.constant.is_some() {
-                    let insn = match inputs.inst {
-                        InputSourceInst::UniqueUse(insn, 0) => Some(insn),
-                        InputSourceInst::Use(insn, 0) => Some(insn),
-                        _ => None,
-                    };
-                    if let Some(insn) = insn {
-                        if let Some(regs) = self.backend.lower(self.lower_ctx, insn) {
-                            assert!(regs.len() == 1);
-                            return regs[0];
-                        }
-                    }
-                }
-            }
-
             self.lower_ctx.put_value_in_regs(val)
         }
 

cranelift/codegen/src/settings.rs

@@ -528,7 +528,6 @@ probestack_strategy = "outline"
 regalloc_checker = false
 regalloc_verbose_logs = false
 enable_alias_analysis = true
-use_egraphs = true
 enable_verifier = true
 is_pic = false
 use_colocated_libcalls = false

cranelift/codegen/src/simple_gvn.rs

@@ -1,149 +0,0 @@
-//! A simple GVN pass.
-
-use crate::cursor::{Cursor, FuncCursor};
-use crate::dominator_tree::DominatorTree;
-use crate::ir::{Function, Inst, InstructionData, Opcode, Type};
-use crate::scoped_hash_map::ScopedHashMap;
-use crate::timing;
-use alloc::vec::Vec;
-use core::cell::{Ref, RefCell};
-use core::hash::{Hash, Hasher};
-
-/// Test whether the given opcode is unsafe to even consider for GVN.
-fn trivially_unsafe_for_gvn(opcode: Opcode) -> bool {
-    opcode.is_call()
-        || opcode.is_branch()
-        || opcode.is_terminator()
-        || opcode.is_return()
-        || opcode.can_store()
-        || (opcode.can_trap() && !opcode.side_effects_idempotent())
-        || (opcode.other_side_effects() && !opcode.side_effects_idempotent())
-}
-
-/// Test that, if the specified instruction is a load, it doesn't have the `readonly` memflag.
-fn is_load_and_not_readonly(inst_data: &InstructionData) -> bool {
-    match *inst_data {
-        InstructionData::Load { flags, .. } => !flags.readonly(),
-        _ => inst_data.opcode().can_load(),
-    }
-}
-
-/// Wrapper around `InstructionData` which implements `Eq` and `Hash`
-#[derive(Clone)]
-struct HashKey<'a, 'f: 'a> {
-    inst: InstructionData,
-    ty: Type,
-    pos: &'a RefCell<FuncCursor<'f>>,
-}
-impl<'a, 'f: 'a> Hash for HashKey<'a, 'f> {
-    fn hash<H: Hasher>(&self, state: &mut H) {
-        let pool = &self.pos.borrow().func.dfg.value_lists;
-        self.inst.hash(state, pool, |value| value);
-        self.ty.hash(state);
-    }
-}
-impl<'a, 'f: 'a> PartialEq for HashKey<'a, 'f> {
-    fn eq(&self, other: &Self) -> bool {
-        let pool = &self.pos.borrow().func.dfg.value_lists;
-        self.inst.eq(&other.inst, pool, |value| value) && self.ty == other.ty
-    }
-}
-impl<'a, 'f: 'a> Eq for HashKey<'a, 'f> {}
-
-/// Perform simple GVN on `func`.
-///
-pub fn do_simple_gvn(func: &mut Function, domtree: &mut DominatorTree) {
-    let _tt = timing::gvn();
-    debug_assert!(domtree.is_valid());
-
-    // Visit blocks in a reverse post-order.
-    //
-    // The RefCell here is a bit ugly since the HashKeys in the ScopedHashMap
-    // need a reference to the function.
-    let pos = RefCell::new(FuncCursor::new(func));
-
-    let mut visible_values: ScopedHashMap<HashKey, Inst> = ScopedHashMap::new();
-    let mut scope_stack: Vec<Inst> = Vec::new();
-
-    for &block in domtree.cfg_postorder().iter().rev() {
-        {
-            // Pop any scopes that we just exited.
-            let layout = &pos.borrow().func.layout;
-            loop {
-                if let Some(current) = scope_stack.last() {
-                    if domtree.dominates(*current, block, layout) {
-                        break;
-                    }
-                } else {
-                    break;
-                }
-                scope_stack.pop();
-                visible_values.decrement_depth();
-            }
-
-            // Push a scope for the current block.
-            scope_stack.push(layout.first_inst(block).unwrap());
-            visible_values.increment_depth();
-        }
-
-        pos.borrow_mut().goto_top(block);
-        while let Some(inst) = {
-            let mut pos = pos.borrow_mut();
-            pos.next_inst()
-        } {
-            // Resolve aliases, particularly aliases we created earlier.
-            pos.borrow_mut().func.dfg.resolve_aliases_in_arguments(inst);
-
-            let func = Ref::map(pos.borrow(), |pos| &pos.func);
-
-            let opcode = func.dfg.insts[inst].opcode();
-
-            if opcode.is_branch() && !opcode.is_terminator() {
-                scope_stack.push(func.layout.next_inst(inst).unwrap());
-                visible_values.increment_depth();
-            }
-
-            if trivially_unsafe_for_gvn(opcode) {
-                continue;
-            }
-
-            // These are split up to separate concerns.
-            if is_load_and_not_readonly(&func.dfg.insts[inst]) {
-                continue;
-            }
-
-            let ctrl_typevar = func.dfg.ctrl_typevar(inst);
-            let key = HashKey {
-                inst: func.dfg.insts[inst],
-                ty: ctrl_typevar,
-                pos: &pos,
-            };
-            use crate::scoped_hash_map::Entry::*;
-            match visible_values.entry(key) {
-                Occupied(entry) => {
-                    #[allow(clippy::debug_assert_with_mut_call)]
-                    {
-                        // Clippy incorrectly believes `&func.layout` should not be used here:
-                        // https://github.com/rust-lang/rust-clippy/issues/4737
-                        debug_assert!(domtree.dominates(*entry.get(), inst, &func.layout));
-                    }
-
-                    // If the redundant instruction is representing the current
-                    // scope, pick a new representative.
-                    let old = scope_stack.last_mut().unwrap();
-                    if *old == inst {
-                        *old = func.layout.next_inst(inst).unwrap();
-                    }
-                    // Replace the redundant instruction and remove it.
-                    drop(func);
-                    let mut pos = pos.borrow_mut();
-                    pos.func.dfg.replace_with_aliases(inst, *entry.get());
-                    pos.remove_inst_and_step_back();
-                }
-                Vacant(entry) => {
-                    entry.insert(inst);
-                }
-            }
-        }
-    }
-}

cranelift/codegen/src/simple_preopt.rs

@@ -1,796 +0,0 @@
-//! A pre-legalization rewriting pass.
-//!
-//! This module provides early-stage optimizations. The optimizations found
-//! should be useful for already well-optimized code.
-
-use crate::cursor::{Cursor, FuncCursor};
-use crate::divconst_magic_numbers::{magic_s32, magic_s64, magic_u32, magic_u64};
-use crate::divconst_magic_numbers::{MS32, MS64, MU32, MU64};
-use crate::ir::{
-    condcodes::IntCC,
-    instructions::Opcode,
-    types::{I128, I32, I64},
-    DataFlowGraph, Function, Inst, InstBuilder, InstructionData, Type, Value,
-};
-use crate::isa::TargetIsa;
-use crate::timing;
-
-#[inline]
-/// Replaces the unique result of the instruction inst to an alias of the given value, and
-/// replaces the instruction with a nop. Can be used only on instructions producing one unique
-/// result, otherwise will assert.
-fn replace_single_result_with_alias(dfg: &mut DataFlowGraph, inst: Inst, value: Value) {
-    // Replace the result value by an alias.
-    let results = dfg.detach_results(inst);
-    debug_assert!(results.len(&dfg.value_lists) == 1);
-    let result = results.get(0, &dfg.value_lists).unwrap();
-    dfg.change_to_alias(result, value);
-
-    // Replace instruction by a nop.
-    dfg.replace(inst).nop();
-}
-
-//----------------------------------------------------------------------
-//
-// Pattern-match helpers and transformation for div and rem by constants.
-
-// Simple math helpers
-
-/// if `x` is a power of two, or the negation thereof, return the power along
-/// with a boolean that indicates whether `x` is negative. Else return None.
-#[inline]
-fn i32_is_power_of_two(x: i32) -> Option<(bool, u32)> {
-    // We have to special-case this because abs(x) isn't representable.
-    if x == -0x8000_0000 {
-        return Some((true, 31));
-    }
-    let abs_x = i32::wrapping_abs(x) as u32;
-    if abs_x.is_power_of_two() {
-        return Some((x < 0, abs_x.trailing_zeros()));
-    }
-    None
-}
-
-/// Same comments as for i32_is_power_of_two apply.
-#[inline]
-fn i64_is_power_of_two(x: i64) -> Option<(bool, u32)> {
-    // We have to special-case this because abs(x) isn't representable.
-    if x == -0x8000_0000_0000_0000 {
-        return Some((true, 63));
-    }
-    let abs_x = i64::wrapping_abs(x) as u64;
-    if abs_x.is_power_of_two() {
-        return Some((x < 0, abs_x.trailing_zeros()));
-    }
-    None
-}
-
-/// Representation of an instruction that can be replaced by a single division/remainder operation
-/// between a left Value operand and a right immediate operand.
-#[derive(Debug)]
-enum DivRemByConstInfo {
-    DivU32(Value, u32),
-    DivU64(Value, u64),
-    DivS32(Value, i32),
-    DivS64(Value, i64),
-    RemU32(Value, u32),
-    RemU64(Value, u64),
-    RemS32(Value, i32),
-    RemS64(Value, i64),
-}
-
-/// Possibly create a DivRemByConstInfo from the given components, by figuring out which, if any,
-/// of the 8 cases apply, and also taking care to sanity-check the immediate.
-fn package_up_divrem_info(
-    value: Value,
-    value_type: Type,
-    imm_i64: i64,
-    is_signed: bool,
-    is_rem: bool,
-) -> Option<DivRemByConstInfo> {
-    let imm_u64 = imm_i64 as u64;
-
-    match (is_signed, value_type) {
-        (false, I32) => {
-            if imm_u64 < 0x1_0000_0000 {
-                if is_rem {
-                    Some(DivRemByConstInfo::RemU32(value, imm_u64 as u32))
-                } else {
-                    Some(DivRemByConstInfo::DivU32(value, imm_u64 as u32))
-                }
-            } else {
-                None
-            }
-        }
-
-        (false, I64) => {
-            // unsigned 64, no range constraint.
-            if is_rem {
-                Some(DivRemByConstInfo::RemU64(value, imm_u64))
-            } else {
-                Some(DivRemByConstInfo::DivU64(value, imm_u64))
-            }
-        }
-
-        (true, I32) => {
-            if imm_u64 <= 0x7fff_ffff || imm_u64 >= 0xffff_ffff_8000_0000 {
-                if is_rem {
-                    Some(DivRemByConstInfo::RemS32(value, imm_u64 as i32))
-                } else {
-                    Some(DivRemByConstInfo::DivS32(value, imm_u64 as i32))
-                }
-            } else {
-                None
-            }
-        }
-
-        (true, I64) => {
-            // signed 64, no range constraint.
-            if is_rem {
-                Some(DivRemByConstInfo::RemS64(value, imm_u64 as i64))
-            } else {
-                Some(DivRemByConstInfo::DivS64(value, imm_u64 as i64))
-            }
-        }
-
-        _ => None,
-    }
-}
-
-/// Examine `inst` to see if it is a div or rem by a constant, and if so return the operands,
-/// signedness, operation size and div-vs-rem-ness in a handy bundle.
-fn get_div_info(inst: Inst, dfg: &DataFlowGraph) -> Option<DivRemByConstInfo> {
-    if let InstructionData::BinaryImm64 { opcode, arg, imm } = dfg.insts[inst] {
-        let (is_signed, is_rem) = match opcode {
-            Opcode::UdivImm => (false, false),
-            Opcode::UremImm => (false, true),
-            Opcode::SdivImm => (true, false),
-            Opcode::SremImm => (true, true),
-            _ => return None,
-        };
-        return package_up_divrem_info(arg, dfg.value_type(arg), imm.into(), is_signed, is_rem);
-    }
-
-    None
-}
-
-/// Actually do the transformation given a bundle containing the relevant information.
-/// `divrem_info` describes a div or rem by a constant, that `pos` currently points at, and `inst`
-/// is the associated instruction.  `inst` is replaced by a sequence of other operations that
-/// calculate the same result. Note that there are various `divrem_info` cases where we cannot do
-/// any transformation, in which case `inst` is left unchanged.
-fn do_divrem_transformation(divrem_info: &DivRemByConstInfo, pos: &mut FuncCursor, inst: Inst) {
-    let is_rem = match *divrem_info {
-        DivRemByConstInfo::DivU32(_, _)
-        | DivRemByConstInfo::DivU64(_, _)
-        | DivRemByConstInfo::DivS32(_, _)
-        | DivRemByConstInfo::DivS64(_, _) => false,
-        DivRemByConstInfo::RemU32(_, _)
-        | DivRemByConstInfo::RemU64(_, _)
-        | DivRemByConstInfo::RemS32(_, _)
-        | DivRemByConstInfo::RemS64(_, _) => true,
-    };
-
-    match *divrem_info {
-        // -------------------- U32 --------------------
-
-        // U32 div, rem by zero: ignore
-        DivRemByConstInfo::DivU32(_n1, 0) | DivRemByConstInfo::RemU32(_n1, 0) => {}
-
-        // U32 div by 1: identity
-        // U32 rem by 1: zero
-        DivRemByConstInfo::DivU32(n1, 1) | DivRemByConstInfo::RemU32(n1, 1) => {
-            if is_rem {
-                pos.func.dfg.replace(inst).iconst(I32, 0);
-            } else {
-                replace_single_result_with_alias(&mut pos.func.dfg, inst, n1);
-            }
-        }
-
-        // U32 div, rem by a power-of-2
-        DivRemByConstInfo::DivU32(n1, d) | DivRemByConstInfo::RemU32(n1, d)
-            if d.is_power_of_two() =>
-        {
-            debug_assert!(d >= 2);
-            // compute k where d == 2^k
-            let k = d.trailing_zeros();
-            debug_assert!(k >= 1 && k <= 31);
-            if is_rem {
-                let mask = (1u64 << k) - 1;
-                pos.func.dfg.replace(inst).band_imm(n1, mask as i64);
-            } else {
-                pos.func.dfg.replace(inst).ushr_imm(n1, k as i64);
-            }
-        }
-
-        // U32 div, rem by non-power-of-2
-        DivRemByConstInfo::DivU32(n1, d) | DivRemByConstInfo::RemU32(n1, d) => {
-            debug_assert!(d >= 3);
-            let MU32 {
-                mul_by,
-                do_add,
-                shift_by,
-            } = magic_u32(d);
-            let qf; // final quotient
-            let q0 = pos.ins().iconst(I32, mul_by as i64);
-            let q1 = pos.ins().umulhi(n1, q0);
-            if do_add {
-                debug_assert!(shift_by >= 1 && shift_by <= 32);
-                let t1 = pos.ins().isub(n1, q1);
-                let t2 = pos.ins().ushr_imm(t1, 1);
-                let t3 = pos.ins().iadd(t2, q1);
-                // I never found any case where shift_by == 1 here.
-                // So there's no attempt to fold out a zero shift.
-                debug_assert_ne!(shift_by, 1);
-                qf = pos.ins().ushr_imm(t3, (shift_by - 1) as i64);
-            } else {
-                debug_assert!(shift_by >= 0 && shift_by <= 31);
-                // Whereas there are known cases here for shift_by == 0.
-                if shift_by > 0 {
-                    qf = pos.ins().ushr_imm(q1, shift_by as i64);
-                } else {
-                    qf = q1;
-                }
-            }
-            // Now qf holds the final quotient. If necessary calculate the
-            // remainder instead.
-            if is_rem {
-                let tt = pos.ins().imul_imm(qf, d as i64);
-                pos.func.dfg.replace(inst).isub(n1, tt);
-            } else {
-                replace_single_result_with_alias(&mut pos.func.dfg, inst, qf);
-            }
-        }
-
-        // -------------------- U64 --------------------
-
-        // U64 div, rem by zero: ignore
-        DivRemByConstInfo::DivU64(_n1, 0) | DivRemByConstInfo::RemU64(_n1, 0) => {}
-
-        // U64 div by 1: identity
-        // U64 rem by 1: zero
-        DivRemByConstInfo::DivU64(n1, 1) | DivRemByConstInfo::RemU64(n1, 1) => {
-            if is_rem {
-                pos.func.dfg.replace(inst).iconst(I64, 0);
-            } else {
-                replace_single_result_with_alias(&mut pos.func.dfg, inst, n1);
-            }
-        }
-
-        // U64 div, rem by a power-of-2
-        DivRemByConstInfo::DivU64(n1, d) | DivRemByConstInfo::RemU64(n1, d)
-            if d.is_power_of_two() =>
-        {
-            debug_assert!(d >= 2);
-            // compute k where d == 2^k
-            let k = d.trailing_zeros();
-            debug_assert!(k >= 1 && k <= 63);
-            if is_rem {
-                let mask = (1u64 << k) - 1;
-                pos.func.dfg.replace(inst).band_imm(n1, mask as i64);
-            } else {
-                pos.func.dfg.replace(inst).ushr_imm(n1, k as i64);
-            }
-        }
-
-        // U64 div, rem by non-power-of-2
-        DivRemByConstInfo::DivU64(n1, d) | DivRemByConstInfo::RemU64(n1, d) => {
-            debug_assert!(d >= 3);
-            let MU64 {
-                mul_by,
-                do_add,
-                shift_by,
-            } = magic_u64(d);
-            let qf; // final quotient
-            let q0 = pos.ins().iconst(I64, mul_by as i64);
-            let q1 = pos.ins().umulhi(n1, q0);
-            if do_add {
-                debug_assert!(shift_by >= 1 && shift_by <= 64);
-                let t1 = pos.ins().isub(n1, q1);
-                let t2 = pos.ins().ushr_imm(t1, 1);
-                let t3 = pos.ins().iadd(t2, q1);
-                // I never found any case where shift_by == 1 here.
-                // So there's no attempt to fold out a zero shift.
-                debug_assert_ne!(shift_by, 1);
-                qf = pos.ins().ushr_imm(t3, (shift_by - 1) as i64);
-            } else {
-                debug_assert!(shift_by >= 0 && shift_by <= 63);
-                // Whereas there are known cases here for shift_by == 0.
-                if shift_by > 0 {
-                    qf = pos.ins().ushr_imm(q1, shift_by as i64);
-                } else {
-                    qf = q1;
-                }
-            }
-            // Now qf holds the final quotient. If necessary calculate the
-            // remainder instead.
-            if is_rem {
-                let tt = pos.ins().imul_imm(qf, d as i64);
-                pos.func.dfg.replace(inst).isub(n1, tt);
-            } else {
-                replace_single_result_with_alias(&mut pos.func.dfg, inst, qf);
-            }
-        }
-
-        // -------------------- S32 --------------------
-
-        // S32 div, rem by zero or -1: ignore
-        DivRemByConstInfo::DivS32(_n1, -1)
-        | DivRemByConstInfo::RemS32(_n1, -1)
-        | DivRemByConstInfo::DivS32(_n1, 0)
-        | DivRemByConstInfo::RemS32(_n1, 0) => {}
-
-        // S32 div by 1: identity
-        // S32 rem by 1: zero
-        DivRemByConstInfo::DivS32(n1, 1) | DivRemByConstInfo::RemS32(n1, 1) => {
-            if is_rem {
-                pos.func.dfg.replace(inst).iconst(I32, 0);
-            } else {
-                replace_single_result_with_alias(&mut pos.func.dfg, inst, n1);
-            }
-        }
-
-        DivRemByConstInfo::DivS32(n1, d) | DivRemByConstInfo::RemS32(n1, d) => {
-            if let Some((is_negative, k)) = i32_is_power_of_two(d) {
-                // k can be 31 only in the case that d is -2^31.
-                debug_assert!(k >= 1 && k <= 31);
-                let t1 = if k - 1 == 0 {
-                    n1
-                } else {
-                    pos.ins().sshr_imm(n1, (k - 1) as i64)
-                };
-                let t2 = pos.ins().ushr_imm(t1, (32 - k) as i64);
-                let t3 = pos.ins().iadd(n1, t2);
-                if is_rem {
-                    // S32 rem by a power-of-2
-                    let t4 = pos.ins().band_imm(t3, i32::wrapping_neg(1 << k) as i64);
-                    // Curiously, we don't care here what the sign of d is.
-                    pos.func.dfg.replace(inst).isub(n1, t4);
-                } else {
-                    // S32 div by a power-of-2
-                    let t4 = pos.ins().sshr_imm(t3, k as i64);
-                    if is_negative {
-                        pos.func.dfg.replace(inst).irsub_imm(t4, 0);
-                    } else {
-                        replace_single_result_with_alias(&mut pos.func.dfg, inst, t4);
-                    }
-                }
-            } else {
-                // S32 div, rem by a non-power-of-2
-                debug_assert!(d < -2 || d > 2);
-                let MS32 { mul_by, shift_by } = magic_s32(d);
-                let q0 = pos.ins().iconst(I32, mul_by as i64);
-                let q1 = pos.ins().smulhi(n1, q0);
-                let q2 = if d > 0 && mul_by < 0 {
-                    pos.ins().iadd(q1, n1)
-                } else if d < 0 && mul_by > 0 {
-                    pos.ins().isub(q1, n1)
-                } else {
-                    q1
-                };
-                debug_assert!(shift_by >= 0 && shift_by <= 31);
-                let q3 = if shift_by == 0 {
-                    q2
-                } else {
-                    pos.ins().sshr_imm(q2, shift_by as i64)
-                };
-                let t1 = pos.ins().ushr_imm(q3, 31);
-                let qf = pos.ins().iadd(q3, t1);
-                // Now qf holds the final quotient. If necessary calculate
-                // the remainder instead.
-                if is_rem {
-                    let tt = pos.ins().imul_imm(qf, d as i64);
-                    pos.func.dfg.replace(inst).isub(n1, tt);
-                } else {
-                    replace_single_result_with_alias(&mut pos.func.dfg, inst, qf);
-                }
-            }
-        }
-
-        // -------------------- S64 --------------------
-
-        // S64 div, rem by zero or -1: ignore
-        DivRemByConstInfo::DivS64(_n1, -1)
-        | DivRemByConstInfo::RemS64(_n1, -1)
-        | DivRemByConstInfo::DivS64(_n1, 0)
-        | DivRemByConstInfo::RemS64(_n1, 0) => {}
-
-        // S64 div by 1: identity
-        // S64 rem by 1: zero
-        DivRemByConstInfo::DivS64(n1, 1) | DivRemByConstInfo::RemS64(n1, 1) => {
-            if is_rem {
-                pos.func.dfg.replace(inst).iconst(I64, 0);
-            } else {
-                replace_single_result_with_alias(&mut pos.func.dfg, inst, n1);
-            }
-        }
-
-        DivRemByConstInfo::DivS64(n1, d) | DivRemByConstInfo::RemS64(n1, d) => {
-            if let Some((is_negative, k)) = i64_is_power_of_two(d) {
-                // k can be 63 only in the case that d is -2^63.
-                debug_assert!(k >= 1 && k <= 63);
-                let t1 = if k - 1 == 0 {
-                    n1
-                } else {
-                    pos.ins().sshr_imm(n1, (k - 1) as i64)
-                };
-                let t2 = pos.ins().ushr_imm(t1, (64 - k) as i64);
-                let t3 = pos.ins().iadd(n1, t2);
-                if is_rem {
-                    // S64 rem by a power-of-2
-                    let t4 = pos.ins().band_imm(t3, i64::wrapping_neg(1 << k));
-                    // Curiously, we don't care here what the sign of d is.
-                    pos.func.dfg.replace(inst).isub(n1, t4);
-                } else {
-                    // S64 div by a power-of-2
-                    let t4 = pos.ins().sshr_imm(t3, k as i64);
-                    if is_negative {
-                        pos.func.dfg.replace(inst).irsub_imm(t4, 0);
-                    } else {
-                        replace_single_result_with_alias(&mut pos.func.dfg, inst, t4);
-                    }
-                }
-            } else {
-                // S64 div, rem by a non-power-of-2
-                debug_assert!(d < -2 || d > 2);
-                let MS64 { mul_by, shift_by } = magic_s64(d);
-                let q0 = pos.ins().iconst(I64, mul_by);
-                let q1 = pos.ins().smulhi(n1, q0);
-                let q2 = if d > 0 && mul_by < 0 {
-                    pos.ins().iadd(q1, n1)
-                } else if d < 0 && mul_by > 0 {
-                    pos.ins().isub(q1, n1)
-                } else {
-                    q1
-                };
-                debug_assert!(shift_by >= 0 && shift_by <= 63);
-                let q3 = if shift_by == 0 {
-                    q2
-                } else {
-                    pos.ins().sshr_imm(q2, shift_by as i64)
-                };
-                let t1 = pos.ins().ushr_imm(q3, 63);
-                let qf = pos.ins().iadd(q3, t1);
-                // Now qf holds the final quotient. If necessary calculate
-                // the remainder instead.
-                if is_rem {
-                    let tt = pos.ins().imul_imm(qf, d);
-                    pos.func.dfg.replace(inst).isub(n1, tt);
-                } else {
-                    replace_single_result_with_alias(&mut pos.func.dfg, inst, qf);
-                }
-            }
-        }
-    }
-}
-
-mod simplify {
-    use super::*;
-    use crate::ir::{
-        dfg::ValueDef,
-        immediates,
-        instructions::Opcode,
-        types::{I16, I32, I8},
-    };
-    use std::marker::PhantomData;
-
-    pub struct PeepholeOptimizer<'a, 'b> {
-        phantom: PhantomData<(&'a (), &'b ())>,
-    }
-
-    pub fn peephole_optimizer<'a, 'b>(_: &dyn TargetIsa) -> PeepholeOptimizer<'a, 'b> {
-        PeepholeOptimizer {
-            phantom: PhantomData,
-        }
-    }
-
-    pub fn apply_all<'a, 'b>(
-        _optimizer: &mut PeepholeOptimizer<'a, 'b>,
-        pos: &mut FuncCursor<'a>,
-        inst: Inst,
-        native_word_width: u32,
-    ) {
-        simplify(pos, inst, native_word_width);
-        branch_opt(pos, inst);
-    }
-
-    #[inline]
-    fn resolve_imm64_value(dfg: &DataFlowGraph, value: Value) -> Option<immediates::Imm64> {
-        if let ValueDef::Result(candidate_inst, _) = dfg.value_def(value) {
-            if let InstructionData::UnaryImm {
-                opcode: Opcode::Iconst,
-                imm,
-            } = dfg.insts[candidate_inst]
-            {
-                return Some(imm);
-            }
-        }
-        None
-    }
-
-    /// Try to transform [(x << N) >> N] into a (un)signed-extending move.
-    /// Returns true if the final instruction has been converted to such a move.
-    fn try_fold_extended_move(
-        pos: &mut FuncCursor,
-        inst: Inst,
-        opcode: Opcode,
-        arg: Value,
-        imm: immediates::Imm64,
-    ) -> bool {
-        if let ValueDef::Result(arg_inst, _) = pos.func.dfg.value_def(arg) {
-            if let InstructionData::BinaryImm64 {
-                opcode: Opcode::IshlImm,
-                arg: prev_arg,
-                imm: prev_imm,
-            } = &pos.func.dfg.insts[arg_inst]
-            {
-                if imm != *prev_imm {
-                    return false;
-                }
-
-                let dest_ty = pos.func.dfg.ctrl_typevar(inst);
-                if dest_ty != pos.func.dfg.ctrl_typevar(arg_inst) || !dest_ty.is_int() {
-                    return false;
-                }
-
-                let imm_bits: i64 = imm.into();
-                let ireduce_ty = match (dest_ty.lane_bits() as i64).wrapping_sub(imm_bits) {
-                    8 => I8,
-                    16 => I16,
-                    32 => I32,
-                    _ => return false,
-                };
-                let ireduce_ty = ireduce_ty.by(dest_ty.lane_count()).unwrap();
-
-                // This becomes a no-op, since ireduce_ty has a smaller lane width than
-                // the argument type (also the destination type).
-                let arg = *prev_arg;
-                let narrower_arg = pos.ins().ireduce(ireduce_ty, arg);
-
-                if opcode == Opcode::UshrImm {
-                    pos.func.dfg.replace(inst).uextend(dest_ty, narrower_arg);
-                } else {
-                    pos.func.dfg.replace(inst).sextend(dest_ty, narrower_arg);
-                }
-                return true;
-            }
-        }
-        false
-    }
-
-    /// Apply basic simplifications.
-    ///
-    /// This folds constants with arithmetic to form `_imm` instructions, and other minor
-    /// simplifications.
-    ///
-    /// Doesn't apply some simplifications if the native word width (in bytes) is smaller than the
-    /// controlling type's width of the instruction. This would result in an illegal instruction that
-    /// would likely be expanded back into an instruction on smaller types with the same initial
-    /// opcode, creating unnecessary churn.
-    fn simplify(pos: &mut FuncCursor, inst: Inst, native_word_width: u32) {
-        match pos.func.dfg.insts[inst] {
-            InstructionData::Binary { opcode, args } => {
-                if let Some(mut imm) = resolve_imm64_value(&pos.func.dfg, args[1]) {
-                    let new_opcode = match opcode {
-                        Opcode::Iadd => Opcode::IaddImm,
-                        Opcode::Imul => Opcode::ImulImm,
-                        Opcode::Sdiv => Opcode::SdivImm,
-                        Opcode::Udiv => Opcode::UdivImm,
-                        Opcode::Srem => Opcode::SremImm,
-                        Opcode::Urem => Opcode::UremImm,
-                        Opcode::Band => Opcode::BandImm,
-                        Opcode::Bor => Opcode::BorImm,
-                        Opcode::Bxor => Opcode::BxorImm,
-                        Opcode::Rotl => Opcode::RotlImm,
-                        Opcode::Rotr => Opcode::RotrImm,
-                        Opcode::Ishl => Opcode::IshlImm,
-                        Opcode::Ushr => Opcode::UshrImm,
-                        Opcode::Sshr => Opcode::SshrImm,
-                        Opcode::Isub => {
-                            imm = imm.wrapping_neg();
-                            Opcode::IaddImm
-                        }
-                        _ => return,
-                    };
-                    let ty = pos.func.dfg.ctrl_typevar(inst);
-                    if ty.bytes() <= native_word_width {
-                        pos.func
-                            .dfg
-                            .replace(inst)
-                            .BinaryImm64(new_opcode, ty, imm, args[0]);
-
-                        // Repeat for BinaryImm simplification.
-                        simplify(pos, inst, native_word_width);
-                    }
-                } else if let Some(imm) = resolve_imm64_value(&pos.func.dfg, args[0]) {
-                    let new_opcode = match opcode {
-                        Opcode::Iadd => Opcode::IaddImm,
-                        Opcode::Imul => Opcode::ImulImm,
-                        Opcode::Band => Opcode::BandImm,
-                        Opcode::Bor => Opcode::BorImm,
-                        Opcode::Bxor => Opcode::BxorImm,
-                        Opcode::Isub => Opcode::IrsubImm,
-                        _ => return,
-                    };
-                    let ty = pos.func.dfg.ctrl_typevar(inst);
-                    if ty.bytes() <= native_word_width {
-                        pos.func
-                            .dfg
-                            .replace(inst)
-                            .BinaryImm64(new_opcode, ty, imm, args[1]);
-                    }
-                }
-            }
-
-            InstructionData::BinaryImm64 { opcode, arg, imm } => {
-                let ty = pos.func.dfg.ctrl_typevar(inst);
-
-                let mut arg = arg;
-                let mut imm = imm;
-                match opcode {
-                    Opcode::IaddImm
-                    | Opcode::ImulImm
-                    | Opcode::BorImm
-                    | Opcode::BandImm
-                    | Opcode::BxorImm => {
-                        // Fold binary_op(C2, binary_op(C1, x)) into binary_op(binary_op(C1, C2), x)
-                        if let ValueDef::Result(arg_inst, _) = pos.func.dfg.value_def(arg) {
-                            if let InstructionData::BinaryImm64 {
-                                opcode: prev_opcode,
-                                arg: prev_arg,
-                                imm: prev_imm,
-                            } = &pos.func.dfg.insts[arg_inst]
-                            {
-                                if opcode == *prev_opcode
-                                    && ty == pos.func.dfg.ctrl_typevar(arg_inst)
-                                {
-                                    let lhs: i64 = imm.into();
-                                    let rhs: i64 = (*prev_imm).into();
-                                    let new_imm = match opcode {
-                                        Opcode::BorImm => lhs | rhs,
-                                        Opcode::BandImm => lhs & rhs,
-                                        Opcode::BxorImm => lhs ^ rhs,
-                                        Opcode::IaddImm => lhs.wrapping_add(rhs),
-                                        Opcode::ImulImm => lhs.wrapping_mul(rhs),
-                                        _ => panic!("can't happen"),
-                                    };
-                                    let new_imm = immediates::Imm64::from(new_imm);
-                                    let new_arg = *prev_arg;
-                                    pos.func
-                                        .dfg
-                                        .replace(inst)
-                                        .BinaryImm64(opcode, ty, new_imm, new_arg);
-                                    imm = new_imm;
-                                    arg = new_arg;
-                                }
-                            }
-                        }
-                    }
-
-                    Opcode::UshrImm | Opcode::SshrImm => {
-                        if pos.func.dfg.ctrl_typevar(inst).bytes() <= native_word_width
-                            && try_fold_extended_move(pos, inst, opcode, arg, imm)
-                        {
-                            return;
-                        }
-                    }
-
-                    _ => {}
-                };
-
-                // Replace operations that are no-ops.
-                match (opcode, imm.into(), ty) {
-                    (Opcode::IaddImm, 0, _)
-                    | (Opcode::ImulImm, 1, _)
-                    | (Opcode::SdivImm, 1, _)
-                    | (Opcode::UdivImm, 1, _)
-                    | (Opcode::BorImm, 0, _)
-                    | (Opcode::BandImm, -1, _)
-                    | (Opcode::BxorImm, 0, _)
-                    | (Opcode::RotlImm, 0, _)
-                    | (Opcode::RotrImm, 0, _)
-                    | (Opcode::IshlImm, 0, _)
-                    | (Opcode::UshrImm, 0, _)
-                    | (Opcode::SshrImm, 0, _) => {
-                        // Alias the result value with the original argument.
-                        replace_single_result_with_alias(&mut pos.func.dfg, inst, arg);
-                    }
-                    (Opcode::ImulImm, 0, ty) | (Opcode::BandImm, 0, ty) if ty != I128 => {
-                        // Replace by zero.
-                        pos.func.dfg.replace(inst).iconst(ty, 0);
-                    }
-                    (Opcode::BorImm, -1, ty) if ty != I128 => {
-                        // Replace by minus one.
-                        pos.func.dfg.replace(inst).iconst(ty, -1);
-                    }
-                    _ => {}
-                }
-            }
-
-            InstructionData::IntCompare { opcode, cond, args } => {
-                debug_assert_eq!(opcode, Opcode::Icmp);
-                if let Some(imm) = resolve_imm64_value(&pos.func.dfg, args[1]) {
-                    if pos.func.dfg.ctrl_typevar(inst).bytes() <= native_word_width {
-                        pos.func.dfg.replace(inst).icmp_imm(cond, args[0], imm);
-                    }
-                }
-            }
-
-            _ => {}
-        }
-    }
-
-    /// Fold comparisons into branch operations when possible.
-    ///
-    /// This matches against operations which compare against zero, then use the
-    /// result in a conditional branch.
-    fn branch_opt(pos: &mut FuncCursor, inst: Inst) {
-        let (cmp_arg, new_then, new_else) = if let InstructionData::Brif {
-            arg: first_arg,
-            blocks: [block_then, block_else],
-            ..
-        } = pos.func.dfg.insts[inst]
-        {
-            let icmp_inst =
-                if let ValueDef::Result(icmp_inst, _) = pos.func.dfg.value_def(first_arg) {
-                    icmp_inst
-                } else {
-                    return;
-                };
-
-            if let InstructionData::IntCompareImm {
-                opcode: Opcode::IcmpImm,
-                arg: cmp_arg,
-                cond: cmp_cond,
-                imm: cmp_imm,
-            } = pos.func.dfg.insts[icmp_inst]
-            {
-                let cmp_imm: i64 = cmp_imm.into();
-                if cmp_imm != 0 {
-                    return;
-                }
-
-                let (new_then, new_else) = match cmp_cond {
-                    IntCC::Equal => (block_else, block_then),
-                    IntCC::NotEqual => (block_then, block_else),
-                    _ => return,
-                };
-
-                (cmp_arg, new_then, new_else)
-            } else {
-                return;
-            }
-        } else {
-            return;
-        };
-
-        if let InstructionData::Brif { arg, blocks, .. } = &mut pos.func.dfg.insts[inst] {
-            *arg = cmp_arg;
-            blocks[0] = new_then;
-            blocks[1] = new_else;
-        } else {
-            unreachable!();
-        }
-    }
-}
-
-/// The main pre-opt pass.
-pub fn do_preopt(func: &mut Function, isa: &dyn TargetIsa) {
-    let _tt = timing::preopt();
-
-    let mut pos = FuncCursor::new(func);
-    let native_word_width = isa.pointer_bytes() as u32;
-    let mut optimizer = simplify::peephole_optimizer(isa);
-
-    while let Some(_) = pos.next_block() {
-        while let Some(inst) = pos.next_inst() {
-            simplify::apply_all(&mut optimizer, &mut pos, inst, native_word_width);
-
-            // Try to transform divide-by-constant into simpler operations.
-            if let Some(divrem_info) = get_div_info(inst, &pos.func.dfg) {
-                do_divrem_transformation(&divrem_info, &mut pos, inst);
-                continue;
-            }
-        }
-    }
-}

cranelift/filetests/filetests/alias/simple-alias.clif

@@ -15,16 +15,15 @@ block0(v0: i64, v1: i32):
     v2 = global_value.i64 gv1
     v3 = load.i32 v2+8
     ;; This should reuse the load above.
-    v4 = global_value.i64 gv1
+    v5 = load.i32 v2+8
-    v5 = load.i32 v4+8
     ; check: v5 -> v3
 
     call fn0(v0)
 
     ;; The second load is redundant wrt the first, but the call above
     ;; is a barrier that prevents reusing v3 or v5.
-    v6 = load.i32 v4+8
+    v6 = load.i32 v2+8
-    v7 = load.i32 v4+8
+    v7 = load.i32 v2+8
     ; check: v7 -> v6
 
     return v3, v5, v6, v7
@@ -44,8 +43,7 @@ block0(v0: i64, v1: i32):
     store.i32 v1, v2+8
 
     ;; This load should pick up the store above.
-    v3 = global_value.i64 gv1
+    v4 = load.i32 v2+8
-    v4 = load.i32 v3+8
     ; check: v4 -> v1
 
     return v4

cranelift/filetests/filetests/egraph/algebraic.clif

@@ -1,6 +1,5 @@
 test optimize
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 
 function %f0(i32) -> i32 {

cranelift/filetests/filetests/egraph/alias_analysis.clif

@@ -1,6 +1,5 @@
 test optimize
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 
 function %f(i64) -> i64 {

cranelift/filetests/filetests/egraph/basic-gvn.clif

@@ -1,6 +1,5 @@
 test optimize
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 
 function %f(i32, i32) -> i32 {

cranelift/filetests/filetests/egraph/bitselect.clif

@@ -1,6 +1,5 @@
 test optimize
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 target aarch64
 target s390x

cranelift/filetests/filetests/egraph/cprop-splat.clif

@@ -1,6 +1,5 @@
 test optimize precise-output
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 
 function %i8x16_1() -> i8x16 {

cranelift/filetests/filetests/egraph/cprop.clif

@@ -1,6 +1,5 @@
 test optimize
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 
 function %f0() -> i8 {

cranelift/filetests/filetests/egraph/i128-opts.clif

@@ -1,6 +1,5 @@
 test optimize
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 
 ; This it a regression test to ensure that we don't insert a iconst.i128 when optimizing bxor.

cranelift/filetests/filetests/egraph/icmp-parameterized.clif

@@ -1,6 +1,5 @@
 test optimize precise-output
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 
 ;; !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

cranelift/filetests/filetests/egraph/icmp.clif

@@ -1,6 +1,5 @@
 test optimize precise-output
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 
 ;; Masking the result of a comparison with 1 always results in the comparison

cranelift/filetests/filetests/egraph/isplit.clif

@@ -1,7 +1,6 @@
 test interpret
 test run
 set opt_level=speed
-set use_egraphs=true
 set enable_llvm_abi_extensions=true
 target x86_64
 target aarch64

cranelift/filetests/filetests/egraph/issue-5405.clif

@@ -1,7 +1,6 @@
 test interpret
 test run
 set opt_level=speed
-set use_egraphs=true
 target aarch64
 
 function %a(i64) -> i8 system_v {

cranelift/filetests/filetests/egraph/issue-5417.clif

@@ -1,6 +1,5 @@
 test compile
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 target aarch64
 target s390x

cranelift/filetests/filetests/egraph/issue-5437.clif

@@ -1,6 +1,5 @@
 test compile
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 target aarch64
 target s390x

cranelift/filetests/filetests/egraph/licm.clif

@@ -1,6 +1,5 @@
 test optimize
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 
 function %f(i32, i32) -> i32 {

cranelift/filetests/filetests/egraph/make-icmp-parameterized-tests.sh

@@ -9,7 +9,6 @@ function main {
     cat << EOF > $out
 test optimize precise-output
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 
 ;; !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

cranelift/filetests/filetests/egraph/misc.clif

@@ -1,6 +1,5 @@
 test optimize
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 
 function %stack_load(i64) -> i64 {

cranelift/filetests/filetests/egraph/mul-pow-2.clif

@@ -1,6 +1,5 @@
 test optimize
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 
 function %f0(i32) -> i32 {

cranelift/filetests/filetests/egraph/multivalue.clif

@@ -1,6 +1,5 @@
 test compile precise-output
 set opt_level=speed
-set use_egraphs=true
 set machine_code_cfg_info=true
 target x86_64
 

cranelift/filetests/filetests/egraph/not_a_load.clif

@@ -1,6 +1,5 @@
 test compile precise-output
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 
 ;; `atomic_rmw` is not a load, but it reports `true` to `.can_load()`. We want

cranelift/filetests/filetests/egraph/remat.clif

@@ -1,6 +1,5 @@
 test optimize
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 
 function %f(i32) -> i32 {

cranelift/filetests/filetests/egraph/select.clif

@@ -1,6 +1,5 @@
 test optimize
 set opt_level=speed
-set use_egraphs=true
 target x86_64
 target aarch64
 target s390x

cranelift/filetests/filetests/isa/aarch64/arithmetic.clif

@@ -542,14 +542,14 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   movz x2, #1
+;   movz x3, #1
-;   sub x0, xzr, x2
+;   sub x0, xzr, x3
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov x2, #1
+;   mov x3, #1
-;   neg x0, x2
+;   neg x0, x3
 ;   ret
 
 function %f30(i8x16) -> i8x16 {

cranelift/filetests/filetests/isa/aarch64/bitops.clif

@@ -515,14 +515,14 @@ block0:
 
 ; VCode:
 ; block0:
-;   movz w0, #255
+;   movz w1, #255
-;   sxtb w0, w0
+;   sxtb w0, w1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov w0, #0xff
+;   mov w1, #0xff
-;   sxtb w0, w0
+;   sxtb w0, w1
 ;   ret
 
 function %sextend_i8() -> i32 {
@@ -534,14 +534,14 @@ block0:
 
 ; VCode:
 ; block0:
-;   movz w0, #255
+;   movz w1, #255
-;   sxtb w0, w0
+;   sxtb w0, w1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov w0, #0xff
+;   mov w1, #0xff
-;   sxtb w0, w0
+;   sxtb w0, w1
 ;   ret
 
 function %bnot_i32(i32) -> i32 {

cranelift/filetests/filetests/isa/aarch64/call.clif

@@ -132,19 +132,18 @@ block0(v0: i8):
 ;   stp fp, lr, [sp, #-16]!
 ;   mov fp, sp
 ; block0:
-;   mov x8, x0
+;   movz w7, #42
 ;   sub sp, sp, #16
 ;   virtual_sp_offset_adjust 16
-;   movz w0, #42
+;   strb w0, [sp]
-;   movz w1, #42
-;   movz w2, #42
-;   movz w3, #42
-;   movz w4, #42
-;   movz w5, #42
-;   movz w6, #42
-;   movz w7, #42
-;   strb w8, [sp]
 ;   load_ext_name x8, TestCase(%g)+0
+;   mov x0, x7
+;   mov x1, x7
+;   mov x2, x7
+;   mov x3, x7
+;   mov x4, x7
+;   mov x5, x7
+;   mov x6, x7
 ;   blr x8
 ;   add sp, sp, #16
 ;   virtual_sp_offset_adjust -16
@@ -156,21 +155,20 @@ block0(v0: i8):
 ;   stp x29, x30, [sp, #-0x10]!
 ;   mov x29, sp
 ; block1: ; offset 0x8
-;   mov x8, x0
-;   sub sp, sp, #0x10
-;   mov w0, #0x2a
-;   mov w1, #0x2a
-;   mov w2, #0x2a
-;   mov w3, #0x2a
-;   mov w4, #0x2a
-;   mov w5, #0x2a
-;   mov w6, #0x2a
 ;   mov w7, #0x2a
-;   sturb w8, [sp]
+;   sub sp, sp, #0x10
-;   ldr x8, #0x3c
+;   sturb w0, [sp]
-;   b #0x44
+;   ldr x8, #0x1c
+;   b #0x24
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
+;   mov x0, x7
+;   mov x1, x7
+;   mov x2, x7
+;   mov x3, x7
+;   mov x4, x7
+;   mov x5, x7
+;   mov x6, x7
 ;   blr x8
 ;   add sp, sp, #0x10
 ;   ldp x29, x30, [sp], #0x10
@@ -184,32 +182,28 @@ block0(v0: i8):
 
 ; VCode:
 ; block0:
-;   mov x9, x0
-;   mov x8, x1
-;   movz w0, #42
-;   movz w1, #42
-;   movz w2, #42
-;   movz w3, #42
-;   movz w4, #42
-;   movz w5, #42
-;   movz w6, #42
 ;   movz w7, #42
-;   strb w9, [x8]
+;   strb w0, [x1]
+;   mov x0, x7
+;   mov x1, x7
+;   mov x2, x7
+;   mov x3, x7
+;   mov x4, x7
+;   mov x5, x7
+;   mov x6, x7
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov x9, x0
-;   mov x8, x1
-;   mov w0, #0x2a
-;   mov w1, #0x2a
-;   mov w2, #0x2a
-;   mov w3, #0x2a
-;   mov w4, #0x2a
-;   mov w5, #0x2a
-;   mov w6, #0x2a
 ;   mov w7, #0x2a
-;   sturb w9, [x8]
+;   sturb w0, [x1]
+;   mov x0, x7
+;   mov x1, x7
+;   mov x2, x7
+;   mov x3, x7
+;   mov x4, x7
+;   mov x5, x7
+;   mov x6, x7
 ;   ret
 
 function %f8() {
@@ -537,10 +531,10 @@ block0(v0: i64):
 ;   mov fp, sp
 ; block0:
 ;   mov x1, x0
-;   movz x0, #42
 ;   movz x2, #42
-;   load_ext_name x6, TestCase(%f11)+0
+;   load_ext_name x4, TestCase(%f11)+0
-;   blr x6
+;   mov x0, x2
+;   blr x4
 ;   ldp fp, lr, [sp], #16
 ;   ret
 ; 
@@ -550,13 +544,13 @@ block0(v0: i64):
 ;   mov x29, sp
 ; block1: ; offset 0x8
 ;   mov x1, x0
-;   mov x0, #0x2a
 ;   mov x2, #0x2a
-;   ldr x6, #0x1c
+;   ldr x4, #0x18
-;   b #0x24
+;   b #0x20
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f11 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   blr x6
+;   mov x0, x2
+;   blr x4
 ;   ldp x29, x30, [sp], #0x10
 ;   ret
 
@@ -592,9 +586,9 @@ block0(v0: i64):
 ; block0:
 ;   mov x2, x0
 ;   movz x3, #42
-;   movz x0, #42
+;   load_ext_name x4, TestCase(%f12)+0
-;   load_ext_name x6, TestCase(%f12)+0
+;   mov x0, x3
-;   blr x6
+;   blr x4
 ;   ldp fp, lr, [sp], #16
 ;   ret
 ; 
@@ -605,12 +599,12 @@ block0(v0: i64):
 ; block1: ; offset 0x8
 ;   mov x2, x0
 ;   mov x3, #0x2a
-;   mov x0, #0x2a
+;   ldr x4, #0x18
-;   ldr x6, #0x1c
+;   b #0x20
-;   b #0x24
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f12 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   blr x6
+;   mov x0, x3
+;   blr x4
 ;   ldp x29, x30, [sp], #0x10
 ;   ret
 
@@ -646,9 +640,9 @@ block0(v0: i64):
 ; block0:
 ;   mov x1, x0
 ;   movz x2, #42
-;   movz x0, #42
+;   load_ext_name x4, TestCase(%f13)+0
-;   load_ext_name x6, TestCase(%f13)+0
+;   mov x0, x2
-;   blr x6
+;   blr x4
 ;   ldp fp, lr, [sp], #16
 ;   ret
 ; 
@@ -659,12 +653,12 @@ block0(v0: i64):
 ; block1: ; offset 0x8
 ;   mov x1, x0
 ;   mov x2, #0x2a
-;   mov x0, #0x2a
+;   ldr x4, #0x18
-;   ldr x6, #0x1c
+;   b #0x20
-;   b #0x24
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f13 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   blr x6
+;   mov x0, x2
+;   blr x4
 ;   ldp x29, x30, [sp], #0x10
 ;   ret
 
@@ -835,16 +829,16 @@ block0:
 ; block0:
 ;   mov x6, x0
 ;   movz w0, #0
-;   movz w4, #1
+;   movz w3, #1
-;   str w4, [x6]
+;   str w3, [x6]
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   mov x6, x0
 ;   mov w0, #0
-;   mov w4, #1
+;   mov w3, #1
-;   stur w4, [x6]
+;   stur w3, [x6]
 ;   ret
 
 function %f17(i64 sret) {

cranelift/filetests/filetests/isa/aarch64/condops.clif

@@ -441,18 +441,18 @@ block0(v0: i128, v1: i8, v2: i8):
 
 ; VCode:
 ; block0:
-;   movz x6, #42
+;   movz x7, #42
 ;   movz x8, #0
-;   subs xzr, x0, x6
+;   subs xzr, x0, x7
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov x6, #0x2a
+;   mov x7, #0x2a
 ;   mov x8, #0
-;   cmp x0, x6
+;   cmp x0, x7
 ;   ccmp x1, x8, #0, eq
 ;   csel x0, x2, x3, eq
 ;   ret
@@ -468,18 +468,18 @@ block0(v0: i128, v1: i16, v2: i16):
 
 ; VCode:
 ; block0:
-;   movz x6, #42
+;   movz x7, #42
 ;   movz x8, #0
-;   subs xzr, x0, x6
+;   subs xzr, x0, x7
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov x6, #0x2a
+;   mov x7, #0x2a
 ;   mov x8, #0
-;   cmp x0, x6
+;   cmp x0, x7
 ;   ccmp x1, x8, #0, eq
 ;   csel x0, x2, x3, eq
 ;   ret
@@ -495,18 +495,18 @@ block0(v0: i128, v1: i32, v2: i32):
 
 ; VCode:
 ; block0:
-;   movz x6, #42
+;   movz x7, #42
 ;   movz x8, #0
-;   subs xzr, x0, x6
+;   subs xzr, x0, x7
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov x6, #0x2a
+;   mov x7, #0x2a
 ;   mov x8, #0
-;   cmp x0, x6
+;   cmp x0, x7
 ;   ccmp x1, x8, #0, eq
 ;   csel x0, x2, x3, eq
 ;   ret
@@ -522,18 +522,18 @@ block0(v0: i128, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   movz x6, #42
+;   movz x7, #42
 ;   movz x8, #0
-;   subs xzr, x0, x6
+;   subs xzr, x0, x7
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov x6, #0x2a
+;   mov x7, #0x2a
 ;   mov x8, #0
-;   cmp x0, x6
+;   cmp x0, x7
 ;   ccmp x1, x8, #0, eq
 ;   csel x0, x2, x3, eq
 ;   ret
@@ -549,9 +549,9 @@ block0(v0: i128, v1: i128, v2: i128):
 
 ; VCode:
 ; block0:
-;   movz x9, #42
+;   movz x10, #42
 ;   movz x11, #0
-;   subs xzr, x0, x9
+;   subs xzr, x0, x10
 ;   ccmp x1, x11, #nzcv, eq
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
@@ -559,9 +559,9 @@ block0(v0: i128, v1: i128, v2: i128):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov x9, #0x2a
+;   mov x10, #0x2a
 ;   mov x11, #0
-;   cmp x0, x9
+;   cmp x0, x10
 ;   ccmp x1, x11, #0, eq
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
@@ -1046,9 +1046,9 @@ block0(v0: i128, v1: i8, v2: i8):
 
 ; VCode:
 ; block0:
-;   movz x6, #42
+;   movz x7, #42
 ;   movz x8, #0
-;   subs xzr, x0, x6
+;   subs xzr, x0, x7
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   csdb
@@ -1056,9 +1056,9 @@ block0(v0: i128, v1: i8, v2: i8):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov x6, #0x2a
+;   mov x7, #0x2a
 ;   mov x8, #0
-;   cmp x0, x6
+;   cmp x0, x7
 ;   ccmp x1, x8, #0, eq
 ;   csel x0, x2, x3, eq
 ;   csdb
@@ -1075,9 +1075,9 @@ block0(v0: i128, v1: i16, v2: i16):
 
 ; VCode:
 ; block0:
-;   movz x6, #42
+;   movz x7, #42
 ;   movz x8, #0
-;   subs xzr, x0, x6
+;   subs xzr, x0, x7
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   csdb
@@ -1085,9 +1085,9 @@ block0(v0: i128, v1: i16, v2: i16):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov x6, #0x2a
+;   mov x7, #0x2a
 ;   mov x8, #0
-;   cmp x0, x6
+;   cmp x0, x7
 ;   ccmp x1, x8, #0, eq
 ;   csel x0, x2, x3, eq
 ;   csdb
@@ -1104,9 +1104,9 @@ block0(v0: i128, v1: i32, v2: i32):
 
 ; VCode:
 ; block0:
-;   movz x6, #42
+;   movz x7, #42
 ;   movz x8, #0
-;   subs xzr, x0, x6
+;   subs xzr, x0, x7
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   csdb
@@ -1114,9 +1114,9 @@ block0(v0: i128, v1: i32, v2: i32):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov x6, #0x2a
+;   mov x7, #0x2a
 ;   mov x8, #0
-;   cmp x0, x6
+;   cmp x0, x7
 ;   ccmp x1, x8, #0, eq
 ;   csel x0, x2, x3, eq
 ;   csdb
@@ -1133,9 +1133,9 @@ block0(v0: i128, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   movz x6, #42
+;   movz x7, #42
 ;   movz x8, #0
-;   subs xzr, x0, x6
+;   subs xzr, x0, x7
 ;   ccmp x1, x8, #nzcv, eq
 ;   csel x0, x2, x3, eq
 ;   csdb
@@ -1143,9 +1143,9 @@ block0(v0: i128, v1: i64, v2: i64):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov x6, #0x2a
+;   mov x7, #0x2a
 ;   mov x8, #0
-;   cmp x0, x6
+;   cmp x0, x7
 ;   ccmp x1, x8, #0, eq
 ;   csel x0, x2, x3, eq
 ;   csdb
@@ -1162,9 +1162,9 @@ block0(v0: i128, v1: i128, v2: i128):
 
 ; VCode:
 ; block0:
-;   movz x9, #42
+;   movz x10, #42
 ;   movz x11, #0
-;   subs xzr, x0, x9
+;   subs xzr, x0, x10
 ;   ccmp x1, x11, #nzcv, eq
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq
@@ -1173,9 +1173,9 @@ block0(v0: i128, v1: i128, v2: i128):
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov x9, #0x2a
+;   mov x10, #0x2a
 ;   mov x11, #0
-;   cmp x0, x9
+;   cmp x0, x10
 ;   ccmp x1, x11, #0, eq
 ;   csel x0, x2, x4, eq
 ;   csel x1, x3, x5, eq

cranelift/filetests/filetests/isa/aarch64/dynamic-slot.clif

@@ -16,9 +16,9 @@ block0:
 ;   mov fp, sp
 ;   sub sp, sp, #16
 ; block0:
-;   mov x1, sp
+;   movz x1, #1
-;   movz x2, #1
+;   mov x2, sp
-;   str x2, [x1]
+;   str x1, [x2]
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
@@ -29,9 +29,9 @@ block0:
 ;   mov x29, sp
 ;   sub sp, sp, #0x10
 ; block1: ; offset 0xc
-;   mov x1, sp
+;   mov x1, #1
-;   mov x2, #1
+;   mov x2, sp
-;   str x2, [x1]
+;   str x1, [x2]
 ;   add sp, sp, #0x10
 ;   ldp x29, x30, [sp], #0x10
 ;   ret
@@ -51,9 +51,9 @@ block0:
 ;   mov fp, sp
 ;   sub sp, sp, #16
 ; block0:
-;   mov x1, sp
+;   movz x1, #1
-;   movz x2, #1
+;   mov x2, sp
-;   str x2, [x1]
+;   str x1, [x2]
 ;   add sp, sp, #16
 ;   ldp fp, lr, [sp], #16
 ;   ret
@@ -64,9 +64,9 @@ block0:
 ;   mov x29, sp
 ;   sub sp, sp, #0x10
 ; block1: ; offset 0xc
-;   mov x1, sp
+;   mov x1, #1
-;   mov x2, #1
+;   mov x2, sp
-;   str x2, [x1]
+;   str x1, [x2]
 ;   add sp, sp, #0x10
 ;   ldp x29, x30, [sp], #0x10
 ;   ret

cranelift/filetests/filetests/isa/aarch64/iconst-icmp-small.clif

@@ -15,19 +15,17 @@ block0:
 
 ; VCode:
 ; block0:
-;   movz w0, #56780
+;   movz w2, #56780
-;   uxth w2, w0
+;   uxth w1, w2
-;   movz w4, #56780
+;   subs wzr, w1, w2, UXTH
-;   subs wzr, w2, w4, UXTH
 ;   cset x0, ne
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov w0, #0xddcc
+;   mov w2, #0xddcc
-;   uxth w2, w0
+;   uxth w1, w2
-;   mov w4, #0xddcc
+;   cmp w1, w2, uxth
-;   cmp w2, w4, uxth
 ;   cset x0, ne
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/simd_load_zero.clif

@@ -11,16 +11,16 @@ block0:
 
 ; VCode:
 ; block0:
-;   movz x1, #1
+;   movz x2, #1
-;   movk x1, x1, #1, LSL #48
+;   movk x2, x2, #1, LSL #48
-;   fmov d0, x1
+;   fmov d0, x2
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov x1, #1
+;   mov x2, #1
-;   movk x1, #1, lsl #48
+;   movk x2, #1, lsl #48
-;   fmov d0, x1
+;   fmov d0, x2
 ;   ret
 
 function %f2() -> i32x4 {
@@ -32,14 +32,14 @@ block0:
 
 ; VCode:
 ; block0:
-;   movz w0, #42679
+;   movz w1, #42679
-;   fmov s0, w0
+;   fmov s0, w1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov w0, #0xa6b7
+;   mov w1, #0xa6b7
-;   fmov s0, w0
+;   fmov s0, w1
 ;   ret
 
 function %f3() -> f32x4 {
@@ -51,14 +51,14 @@ block0:
 
 ; VCode:
 ; block0:
-;   fmov s0, #1
+;   fmov s1, #1
-;   fmov s0, s0
+;   fmov s0, s1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   fmov s0, #1.00000000
+;   fmov s1, #1.00000000
-;   fmov s0, s0
+;   fmov s0, s1
 ;   ret
 
 function %f4() -> f64x2 {
@@ -70,13 +70,13 @@ block0:
 
 ; VCode:
 ; block0:
-;   fmov d0, #1
+;   fmov d1, #1
-;   fmov d0, d0
+;   fmov d0, d1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   fmov d0, #1.00000000
+;   fmov d1, #1.00000000
-;   fmov d0, d0
+;   fmov d0, d1
 ;   ret
 

cranelift/filetests/filetests/isa/aarch64/stack.clif

@@ -370,147 +370,167 @@ block0(v0: i8):
 ;   stp x23, x24, [sp, #-16]!
 ;   stp x21, x22, [sp, #-16]!
 ;   stp x19, x20, [sp, #-16]!
-;   sub sp, sp, #1152
+;   sub sp, sp, #1216
 ; block0:
 ;   str x0, [sp, #1000]
-;   movz x6, #2
+;   movz x8, #2
-;   add x9, x6, #1
+;   str x8, [sp, #1008]
-;   str x9, [sp, #1136]
+;   movz x8, #4
-;   movz x6, #4
+;   movz x9, #6
-;   add x10, x6, #3
+;   movz x10, #8
-;   str x10, [sp, #1128]
+;   movz x11, #10
-;   movz x6, #6
+;   movz x12, #12
-;   add x11, x6, #5
+;   movz x13, #14
-;   str x11, [sp, #1120]
+;   movz x14, #16
-;   movz x6, #8
+;   movz x15, #18
-;   add x12, x6, #7
+;   movz x1, #20
-;   str x12, [sp, #1112]
+;   movz x2, #22
-;   movz x6, #10
+;   movz x3, #24
-;   add x13, x6, #9
+;   movz x4, #26
-;   str x13, [sp, #1104]
+;   movz x5, #28
-;   movz x6, #12
+;   movz x6, #30
-;   add x14, x6, #11
+;   movz x23, #32
-;   str x14, [sp, #1096]
+;   movz x24, #34
-;   movz x6, #14
+;   movz x25, #36
-;   add x15, x6, #13
+;   movz x26, #38
-;   str x15, [sp, #1088]
+;   movz x27, #30
-;   movz x6, #16
+;   movz x28, #32
-;   add x1, x6, #15
+;   movz x21, #34
-;   str x1, [sp, #1080]
+;   movz x19, #36
-;   movz x6, #18
+;   movz x20, #38
-;   add x2, x6, #17
+;   movz x22, #30
-;   str x2, [sp, #1072]
+;   movz x0, #32
-;   movz x6, #20
+;   movz x7, #34
-;   add x3, x6, #19
+;   str x7, [sp, #1208]
-;   str x3, [sp, #1064]
+;   movz x7, #36
-;   movz x6, #22
+;   str x7, [sp, #1200]
-;   add x4, x6, #21
+;   movz x7, #38
-;   str x4, [sp, #1056]
+;   str x7, [sp, #1192]
-;   movz x6, #24
+;   movz x7, #30
-;   add x5, x6, #23
+;   str x7, [sp, #1184]
-;   str x5, [sp, #1048]
+;   movz x7, #32
-;   movz x6, #26
+;   str x7, [sp, #1176]
-;   add x6, x6, #25
+;   movz x7, #34
-;   str x6, [sp, #1040]
+;   str x7, [sp, #1168]
-;   movz x6, #28
+;   movz x7, #36
-;   add x7, x6, #27
+;   str x7, [sp, #1160]
+;   movz x7, #38
+;   str x7, [sp, #1152]
+;   ldr x7, [sp, #1008]
+;   add x7, x7, #1
+;   str x7, [sp, #1144]
+;   add x7, x8, #3
+;   str x7, [sp, #1136]
+;   add x7, x9, #5
+;   str x7, [sp, #1128]
+;   add x7, x10, #7
+;   str x7, [sp, #1120]
+;   add x7, x11, #9
+;   str x7, [sp, #1112]
+;   add x7, x12, #11
+;   str x7, [sp, #1104]
+;   add x7, x13, #13
+;   str x7, [sp, #1096]
+;   add x7, x14, #15
+;   str x7, [sp, #1088]
+;   add x7, x15, #17
+;   str x7, [sp, #1080]
+;   add x7, x1, #19
+;   str x7, [sp, #1072]
+;   add x7, x2, #21
+;   str x7, [sp, #1064]
+;   add x7, x3, #23
+;   str x7, [sp, #1056]
+;   add x7, x4, #25
+;   str x7, [sp, #1048]
+;   add x7, x5, #27
+;   str x7, [sp, #1040]
+;   add x7, x6, #29
 ;   str x7, [sp, #1032]
-;   movz x6, #30
+;   add x7, x23, #31
-;   add x24, x6, #29
+;   str x7, [sp, #1024]
-;   str x24, [sp, #1024]
+;   add x7, x24, #33
-;   movz x6, #32
+;   str x7, [sp, #1016]
-;   add x25, x6, #31
+;   add x7, x25, #35
-;   str x25, [sp, #1016]
+;   str x7, [sp, #1008]
-;   movz x6, #34
+;   add x26, x26, #37
-;   add x26, x6, #33
+;   add x27, x27, #39
-;   movz x6, #36
+;   add x28, x28, #31
-;   add x27, x6, #35
+;   add x21, x21, #33
-;   str x27, [sp, #1008]
+;   add x19, x19, #35
-;   movz x6, #38
+;   add x20, x20, #37
-;   add x27, x6, #37
+;   add x22, x22, #39
-;   movz x6, #30
+;   add x0, x0, #31
-;   add x28, x6, #39
+;   ldr x7, [sp, #1208]
-;   movz x6, #32
+;   add x7, x7, #33
-;   add x21, x6, #31
+;   ldr x9, [sp, #1200]
-;   movz x6, #34
+;   add x8, x9, #35
-;   add x19, x6, #33
+;   ldr x12, [sp, #1192]
-;   movz x6, #36
+;   add x9, x12, #37
-;   add x20, x6, #35
+;   ldr x15, [sp, #1184]
-;   movz x6, #38
+;   add x10, x15, #39
-;   add x22, x6, #37
+;   ldr x2, [sp, #1176]
-;   movz x6, #30
+;   add x11, x2, #31
-;   add x23, x6, #39
+;   ldr x5, [sp, #1168]
-;   movz x6, #32
+;   add x12, x5, #33
-;   add x0, x6, #31
+;   ldr x13, [sp, #1160]
-;   movz x6, #34
+;   add x13, x13, #35
-;   add x8, x6, #33
+;   ldr x14, [sp, #1152]
-;   movz x6, #36
+;   add x14, x14, #37
-;   add x9, x6, #35
+;   ldr x15, [sp, #1144]
-;   movz x6, #38
+;   add x15, x15, #39
-;   add x10, x6, #37
+;   ldr x3, [sp, #1128]
-;   movz x6, #30
-;   add x11, x6, #39
-;   movz x6, #32
-;   add x12, x6, #31
-;   movz x6, #34
-;   add x13, x6, #33
-;   movz x6, #36
-;   add x14, x6, #35
-;   movz x6, #38
-;   add x15, x6, #37
 ;   ldr x1, [sp, #1136]
-;   add x1, x1, #39
+;   add x1, x1, x3
-;   ldr x3, [sp, #1120]
+;   ldr x2, [sp, #1112]
-;   ldr x2, [sp, #1128]
+;   ldr x6, [sp, #1120]
-;   add x2, x2, x3
+;   add x2, x6, x2
-;   ldr x3, [sp, #1104]
+;   ldr x3, [sp, #1096]
-;   ldr x6, [sp, #1112]
+;   ldr x4, [sp, #1104]
-;   add x3, x6, x3
+;   add x3, x4, x3
-;   ldr x4, [sp, #1088]
+;   ldr x4, [sp, #1080]
-;   ldr x5, [sp, #1096]
+;   ldr x5, [sp, #1088]
 ;   add x4, x5, x4
-;   ldr x5, [sp, #1072]
+;   ldr x5, [sp, #1064]
-;   ldr x6, [sp, #1080]
+;   ldr x6, [sp, #1072]
 ;   add x5, x6, x5
-;   ldr x7, [sp, #1056]
+;   ldr x6, [sp, #1048]
-;   ldr x6, [sp, #1064]
+;   ldr x23, [sp, #1056]
-;   add x6, x6, x7
+;   add x6, x23, x6
-;   ldr x7, [sp, #1040]
+;   ldr x23, [sp, #1032]
-;   ldr x24, [sp, #1048]
+;   ldr x24, [sp, #1040]
-;   add x7, x24, x7
+;   add x23, x24, x23
-;   ldr x24, [sp, #1024]
-;   ldr x25, [sp, #1032]
-;   add x24, x25, x24
 ;   ldr x25, [sp, #1016]
+;   ldr x24, [sp, #1024]
+;   add x24, x24, x25
+;   ldr x25, [sp, #1008]
 ;   add x25, x25, x26
-;   ldr x26, [sp, #1008]
+;   add x26, x27, x28
-;   add x26, x26, x27
+;   add x27, x21, x19
-;   add x27, x28, x21
+;   add x28, x20, x22
-;   add x28, x19, x20
+;   add x7, x0, x7
-;   add x23, x22, x23
-;   add x8, x0, x8
-;   add x9, x9, x10
-;   add x10, x11, x12
-;   add x11, x13, x14
-;   add x12, x15, x1
-;   add x13, x2, x3
-;   add x14, x4, x5
-;   add x7, x6, x7
-;   add x15, x24, x25
-;   add x0, x26, x27
-;   add x1, x28, x23
 ;   add x8, x8, x9
 ;   add x9, x10, x11
 ;   add x10, x12, x13
-;   add x7, x14, x7
+;   add x11, x14, x15
+;   add x12, x1, x2
+;   add x13, x3, x4
+;   add x14, x5, x6
+;   add x15, x23, x24
+;   add x0, x25, x26
+;   add x1, x27, x28
+;   add x7, x7, x8
+;   add x8, x9, x10
+;   add x9, x11, x12
+;   add x10, x13, x14
 ;   add x11, x15, x0
-;   add x8, x1, x8
+;   add x7, x1, x7
-;   add x9, x9, x10
-;   add x7, x7, x11
 ;   add x8, x8, x9
-;   add x1, x7, x8
+;   add x9, x10, x11
+;   add x7, x7, x8
+;   add x1, x9, x7
 ;   ldr x0, [sp, #1000]
-;   add sp, sp, #1152
+;   add sp, sp, #1216
 ;   ldp x19, x20, [sp], #16
 ;   ldp x21, x22, [sp], #16
 ;   ldp x23, x24, [sp], #16
@@ -528,147 +548,167 @@ block0(v0: i8):
 ;   stp x23, x24, [sp, #-0x10]!
 ;   stp x21, x22, [sp, #-0x10]!
 ;   stp x19, x20, [sp, #-0x10]!
-;   sub sp, sp, #0x480
+;   sub sp, sp, #0x4c0
 ; block1: ; offset 0x20
 ;   str x0, [sp, #0x3e8]
-;   mov x6, #2
+;   mov x8, #2
-;   add x9, x6, #1
+;   str x8, [sp, #0x3f0]
-;   str x9, [sp, #0x470]
+;   mov x8, #4
-;   mov x6, #4
+;   mov x9, #6
-;   add x10, x6, #3
+;   mov x10, #8
-;   str x10, [sp, #0x468]
+;   mov x11, #0xa
-;   mov x6, #6
+;   mov x12, #0xc
-;   add x11, x6, #5
+;   mov x13, #0xe
-;   str x11, [sp, #0x460]
+;   mov x14, #0x10
-;   mov x6, #8
+;   mov x15, #0x12
-;   add x12, x6, #7
+;   mov x1, #0x14
-;   str x12, [sp, #0x458]
+;   mov x2, #0x16
-;   mov x6, #0xa
+;   mov x3, #0x18
-;   add x13, x6, #9
+;   mov x4, #0x1a
-;   str x13, [sp, #0x450]
+;   mov x5, #0x1c
-;   mov x6, #0xc
+;   mov x6, #0x1e
-;   add x14, x6, #0xb
+;   mov x23, #0x20
-;   str x14, [sp, #0x448]
+;   mov x24, #0x22
-;   mov x6, #0xe
+;   mov x25, #0x24
-;   add x15, x6, #0xd
+;   mov x26, #0x26
-;   str x15, [sp, #0x440]
+;   mov x27, #0x1e
-;   mov x6, #0x10
+;   mov x28, #0x20
-;   add x1, x6, #0xf
+;   mov x21, #0x22
-;   str x1, [sp, #0x438]
+;   mov x19, #0x24
-;   mov x6, #0x12
+;   mov x20, #0x26
-;   add x2, x6, #0x11
+;   mov x22, #0x1e
-;   str x2, [sp, #0x430]
+;   mov x0, #0x20
-;   mov x6, #0x14
+;   mov x7, #0x22
-;   add x3, x6, #0x13
+;   str x7, [sp, #0x4b8]
-;   str x3, [sp, #0x428]
+;   mov x7, #0x24
-;   mov x6, #0x16
+;   str x7, [sp, #0x4b0]
-;   add x4, x6, #0x15
+;   mov x7, #0x26
-;   str x4, [sp, #0x420]
+;   str x7, [sp, #0x4a8]
-;   mov x6, #0x18
+;   mov x7, #0x1e
-;   add x5, x6, #0x17
+;   str x7, [sp, #0x4a0]
-;   str x5, [sp, #0x418]
+;   mov x7, #0x20
-;   mov x6, #0x1a
+;   str x7, [sp, #0x498]
-;   add x6, x6, #0x19
+;   mov x7, #0x22
-;   str x6, [sp, #0x410]
+;   str x7, [sp, #0x490]
-;   mov x6, #0x1c
+;   mov x7, #0x24
-;   add x7, x6, #0x1b
+;   str x7, [sp, #0x488]
+;   mov x7, #0x26
+;   str x7, [sp, #0x480]
+;   ldr x7, [sp, #0x3f0]
+;   add x7, x7, #1
+;   str x7, [sp, #0x478]
+;   add x7, x8, #3
+;   str x7, [sp, #0x470]
+;   add x7, x9, #5
+;   str x7, [sp, #0x468]
+;   add x7, x10, #7
+;   str x7, [sp, #0x460]
+;   add x7, x11, #9
+;   str x7, [sp, #0x458]
+;   add x7, x12, #0xb
+;   str x7, [sp, #0x450]
+;   add x7, x13, #0xd
+;   str x7, [sp, #0x448]
+;   add x7, x14, #0xf
+;   str x7, [sp, #0x440]
+;   add x7, x15, #0x11
+;   str x7, [sp, #0x438]
+;   add x7, x1, #0x13
+;   str x7, [sp, #0x430]
+;   add x7, x2, #0x15
+;   str x7, [sp, #0x428]
+;   add x7, x3, #0x17
+;   str x7, [sp, #0x420]
+;   add x7, x4, #0x19
+;   str x7, [sp, #0x418]
+;   add x7, x5, #0x1b
+;   str x7, [sp, #0x410]
+;   add x7, x6, #0x1d
 ;   str x7, [sp, #0x408]
-;   mov x6, #0x1e
+;   add x7, x23, #0x1f
-;   add x24, x6, #0x1d
+;   str x7, [sp, #0x400]
-;   str x24, [sp, #0x400]
+;   add x7, x24, #0x21
-;   mov x6, #0x20
+;   str x7, [sp, #0x3f8]
-;   add x25, x6, #0x1f
+;   add x7, x25, #0x23
-;   str x25, [sp, #0x3f8]
+;   str x7, [sp, #0x3f0]
-;   mov x6, #0x22
+;   add x26, x26, #0x25
-;   add x26, x6, #0x21
+;   add x27, x27, #0x27
-;   mov x6, #0x24
+;   add x28, x28, #0x1f
-;   add x27, x6, #0x23
+;   add x21, x21, #0x21
-;   str x27, [sp, #0x3f0]
+;   add x19, x19, #0x23
-;   mov x6, #0x26
+;   add x20, x20, #0x25
-;   add x27, x6, #0x25
+;   add x22, x22, #0x27
-;   mov x6, #0x1e
+;   add x0, x0, #0x1f
-;   add x28, x6, #0x27
+;   ldr x7, [sp, #0x4b8]
-;   mov x6, #0x20
+;   add x7, x7, #0x21
-;   add x21, x6, #0x1f
+;   ldr x9, [sp, #0x4b0]
-;   mov x6, #0x22
+;   add x8, x9, #0x23
-;   add x19, x6, #0x21
+;   ldr x12, [sp, #0x4a8]
-;   mov x6, #0x24
+;   add x9, x12, #0x25
-;   add x20, x6, #0x23
+;   ldr x15, [sp, #0x4a0]
-;   mov x6, #0x26
+;   add x10, x15, #0x27
-;   add x22, x6, #0x25
+;   ldr x2, [sp, #0x498]
-;   mov x6, #0x1e
+;   add x11, x2, #0x1f
-;   add x23, x6, #0x27
+;   ldr x5, [sp, #0x490]
-;   mov x6, #0x20
+;   add x12, x5, #0x21
-;   add x0, x6, #0x1f
+;   ldr x13, [sp, #0x488]
-;   mov x6, #0x22
+;   add x13, x13, #0x23
-;   add x8, x6, #0x21
+;   ldr x14, [sp, #0x480]
-;   mov x6, #0x24
+;   add x14, x14, #0x25
-;   add x9, x6, #0x23
+;   ldr x15, [sp, #0x478]
-;   mov x6, #0x26
+;   add x15, x15, #0x27
-;   add x10, x6, #0x25
+;   ldr x3, [sp, #0x468]
-;   mov x6, #0x1e
-;   add x11, x6, #0x27
-;   mov x6, #0x20
-;   add x12, x6, #0x1f
-;   mov x6, #0x22
-;   add x13, x6, #0x21
-;   mov x6, #0x24
-;   add x14, x6, #0x23
-;   mov x6, #0x26
-;   add x15, x6, #0x25
 ;   ldr x1, [sp, #0x470]
-;   add x1, x1, #0x27
+;   add x1, x1, x3
-;   ldr x3, [sp, #0x460]
+;   ldr x2, [sp, #0x458]
-;   ldr x2, [sp, #0x468]
+;   ldr x6, [sp, #0x460]
-;   add x2, x2, x3
+;   add x2, x6, x2
-;   ldr x3, [sp, #0x450]
+;   ldr x3, [sp, #0x448]
-;   ldr x6, [sp, #0x458]
+;   ldr x4, [sp, #0x450]
-;   add x3, x6, x3
+;   add x3, x4, x3
-;   ldr x4, [sp, #0x440]
+;   ldr x4, [sp, #0x438]
-;   ldr x5, [sp, #0x448]
+;   ldr x5, [sp, #0x440]
 ;   add x4, x5, x4
-;   ldr x5, [sp, #0x430]
+;   ldr x5, [sp, #0x428]
-;   ldr x6, [sp, #0x438]
+;   ldr x6, [sp, #0x430]
 ;   add x5, x6, x5
-;   ldr x7, [sp, #0x420]
+;   ldr x6, [sp, #0x418]
-;   ldr x6, [sp, #0x428]
+;   ldr x23, [sp, #0x420]
-;   add x6, x6, x7
+;   add x6, x23, x6
-;   ldr x7, [sp, #0x410]
+;   ldr x23, [sp, #0x408]
-;   ldr x24, [sp, #0x418]
+;   ldr x24, [sp, #0x410]
-;   add x7, x24, x7
+;   add x23, x24, x23
-;   ldr x24, [sp, #0x400]
-;   ldr x25, [sp, #0x408]
-;   add x24, x25, x24
 ;   ldr x25, [sp, #0x3f8]
+;   ldr x24, [sp, #0x400]
+;   add x24, x24, x25
+;   ldr x25, [sp, #0x3f0]
 ;   add x25, x25, x26
-;   ldr x26, [sp, #0x3f0]
+;   add x26, x27, x28
-;   add x26, x26, x27
+;   add x27, x21, x19
-;   add x27, x28, x21
+;   add x28, x20, x22
-;   add x28, x19, x20
+;   add x7, x0, x7
-;   add x23, x22, x23
-;   add x8, x0, x8
-;   add x9, x9, x10
-;   add x10, x11, x12
-;   add x11, x13, x14
-;   add x12, x15, x1
-;   add x13, x2, x3
-;   add x14, x4, x5
-;   add x7, x6, x7
-;   add x15, x24, x25
-;   add x0, x26, x27
-;   add x1, x28, x23
 ;   add x8, x8, x9
 ;   add x9, x10, x11
 ;   add x10, x12, x13
-;   add x7, x14, x7
+;   add x11, x14, x15
+;   add x12, x1, x2
+;   add x13, x3, x4
+;   add x14, x5, x6
+;   add x15, x23, x24
+;   add x0, x25, x26
+;   add x1, x27, x28
+;   add x7, x7, x8
+;   add x8, x9, x10
+;   add x9, x11, x12
+;   add x10, x13, x14
 ;   add x11, x15, x0
-;   add x8, x1, x8
+;   add x7, x1, x7
-;   add x9, x9, x10
-;   add x7, x7, x11
 ;   add x8, x8, x9
-;   add x1, x7, x8
+;   add x9, x10, x11
+;   add x7, x7, x8
+;   add x1, x9, x7
 ;   ldr x0, [sp, #0x3e8]
-;   add sp, sp, #0x480
+;   add sp, sp, #0x4c0
 ;   ldp x19, x20, [sp], #0x10
 ;   ldp x21, x22, [sp], #0x10
 ;   ldp x23, x24, [sp], #0x10

cranelift/filetests/filetests/isa/aarch64/uadd_overflow_trap.clif

@@ -10,15 +10,15 @@ block0(v0: i32):
 
 ; VCode:
 ; block0:
-;   movz w2, #127
+;   movz w3, #127
-;   adds w0, w0, w2
+;   adds w0, w0, w3
 ;   b.hs #trap=user0
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov w2, #0x7f
+;   mov w3, #0x7f
-;   adds w0, w0, w2
+;   adds w0, w0, w3
 ;   b.hs #0x10
 ;   ret
 ;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: user0
@@ -32,15 +32,15 @@ block0(v0: i32):
 
 ; VCode:
 ; block0:
-;   movz w2, #127
+;   movz w3, #127
-;   adds w0, w2, w0
+;   adds w0, w3, w0
 ;   b.hs #trap=user0
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov w2, #0x7f
+;   mov w3, #0x7f
-;   adds w0, w2, w0
+;   adds w0, w3, w0
 ;   b.hs #0x10
 ;   ret
 ;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: user0
@@ -73,15 +73,15 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   movz x2, #127
+;   movz x3, #127
-;   adds x0, x0, x2
+;   adds x0, x0, x3
 ;   b.hs #trap=user0
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov x2, #0x7f
+;   mov x3, #0x7f
-;   adds x0, x0, x2
+;   adds x0, x0, x3
 ;   b.hs #0x10
 ;   ret
 ;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: user0
@@ -95,15 +95,15 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   movz x2, #127
+;   movz x3, #127
-;   adds x0, x2, x0
+;   adds x0, x3, x0
 ;   b.hs #trap=user0
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mov x2, #0x7f
+;   mov x3, #0x7f
-;   adds x0, x2, x0
+;   adds x0, x3, x0
 ;   b.hs #0x10
 ;   ret
 ;   .byte 0x1f, 0xc1, 0x00, 0x00 ; trap: user0

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0x1000_offset.wat

@@ -43,8 +43,8 @@
 ;; block0:
 ;;   mov w9, w0
 ;;   ldr x10, [x2, #8]
-;;   movn x8, #4099
+;;   movn x11, #4099
-;;   add x10, x10, x8
+;;   add x10, x10, x11
 ;;   subs xzr, x9, x10
 ;;   b.hi label3 ; b label1
 ;; block1:
@@ -61,8 +61,8 @@
 ;; block0:
 ;;   mov w9, w0
 ;;   ldr x10, [x1, #8]
-;;   movn x8, #4099
+;;   movn x11, #4099
-;;   add x10, x10, x8
+;;   add x10, x10, x11
 ;;   subs xzr, x9, x10
 ;;   b.hi label3 ; b label1
 ;; block1:

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat

@@ -42,11 +42,11 @@
 ;; function u0:0:
 ;; block0:
 ;;   mov w10, w0
-;;   movn w9, #65531
+;;   movn w11, #65531
-;;   adds x11, x10, x9
+;;   adds x10, x10, x11
 ;;   b.hs #trap=heap_oob
-;;   ldr x12, [x2, #8]
+;;   ldr x11, [x2, #8]
-;;   subs xzr, x11, x12
+;;   subs xzr, x10, x11
 ;;   b.hi label3 ; b label1
 ;; block1:
 ;;   ldr x13, [x2]
@@ -62,11 +62,11 @@
 ;; function u0:1:
 ;; block0:
 ;;   mov w10, w0
-;;   movn w9, #65531
+;;   movn w11, #65531
-;;   adds x11, x10, x9
+;;   adds x10, x10, x11
 ;;   b.hs #trap=heap_oob
-;;   ldr x12, [x1, #8]
+;;   ldr x11, [x1, #8]
-;;   subs xzr, x11, x12
+;;   subs xzr, x10, x11
 ;;   b.hi label3 ; b label1
 ;; block1:
 ;;   ldr x13, [x1]

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0x1000_offset.wat

@@ -43,8 +43,8 @@
 ;; block0:
 ;;   mov w9, w0
 ;;   ldr x10, [x2, #8]
-;;   movn x8, #4096
+;;   movn x11, #4096
-;;   add x10, x10, x8
+;;   add x10, x10, x11
 ;;   subs xzr, x9, x10
 ;;   b.hi label3 ; b label1
 ;; block1:
@@ -61,8 +61,8 @@
 ;; block0:
 ;;   mov w9, w0
 ;;   ldr x10, [x1, #8]
-;;   movn x8, #4096
+;;   movn x11, #4096
-;;   add x10, x10, x8
+;;   add x10, x10, x11
 ;;   subs xzr, x9, x10
 ;;   b.hi label3 ; b label1
 ;; block1:

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i32_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat

@@ -42,11 +42,11 @@
 ;; function u0:0:
 ;; block0:
 ;;   mov w10, w0
-;;   movn w9, #65534
+;;   movn w11, #65534
-;;   adds x11, x10, x9
+;;   adds x10, x10, x11
 ;;   b.hs #trap=heap_oob
-;;   ldr x12, [x2, #8]
+;;   ldr x11, [x2, #8]
-;;   subs xzr, x11, x12
+;;   subs xzr, x10, x11
 ;;   b.hi label3 ; b label1
 ;; block1:
 ;;   ldr x13, [x2]
@@ -62,11 +62,11 @@
 ;; function u0:1:
 ;; block0:
 ;;   mov w10, w0
-;;   movn w9, #65534
+;;   movn w11, #65534
-;;   adds x11, x10, x9
+;;   adds x10, x10, x11
 ;;   b.hs #trap=heap_oob
-;;   ldr x12, [x1, #8]
+;;   ldr x11, [x1, #8]
-;;   subs xzr, x11, x12
+;;   subs xzr, x10, x11
 ;;   b.hi label3 ; b label1
 ;; block1:
 ;;   ldr x13, [x1]

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat

@@ -46,11 +46,11 @@
 ;;   sub x11, x11, #4
 ;;   ldr x12, [x2]
 ;;   add x12, x12, x0, UXTW
-;;   movz x9, #0
+;;   movz x13, #0
 ;;   subs xzr, x10, x11
-;;   csel x12, x9, x12, hi
+;;   csel x11, x13, x12, hi
 ;;   csdb
-;;   str w1, [x12]
+;;   str w1, [x11]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -62,11 +62,11 @@
 ;;   sub x11, x11, #4
 ;;   ldr x12, [x1]
 ;;   add x12, x12, x0, UXTW
-;;   movz x9, #0
+;;   movz x13, #0
 ;;   subs xzr, x10, x11
-;;   csel x12, x9, x12, hi
+;;   csel x11, x13, x12, hi
 ;;   csdb
-;;   ldr w0, [x12]
+;;   ldr w0, [x11]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat

@@ -43,16 +43,16 @@
 ;; block0:
 ;;   mov w12, w0
 ;;   ldr x13, [x2, #8]
-;;   movn x11, #4099
+;;   movn x14, #4099
-;;   add x13, x13, x11
+;;   add x13, x13, x14
 ;;   ldr x14, [x2]
 ;;   add x14, x14, x0, UXTW
 ;;   add x14, x14, #4096
-;;   movz x11, #0
+;;   movz x15, #0
 ;;   subs xzr, x12, x13
-;;   csel x14, x11, x14, hi
+;;   csel x13, x15, x14, hi
 ;;   csdb
-;;   str w1, [x14]
+;;   str w1, [x13]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -61,16 +61,16 @@
 ;; block0:
 ;;   mov w12, w0
 ;;   ldr x13, [x1, #8]
-;;   movn x11, #4099
+;;   movn x14, #4099
-;;   add x13, x13, x11
+;;   add x13, x13, x14
 ;;   ldr x14, [x1]
 ;;   add x14, x14, x0, UXTW
 ;;   add x14, x14, #4096
-;;   movz x11, #0
+;;   movz x15, #0
 ;;   subs xzr, x12, x13
-;;   csel x14, x11, x14, hi
+;;   csel x13, x15, x14, hi
 ;;   csdb
-;;   ldr w0, [x14]
+;;   ldr w0, [x13]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat

@@ -42,19 +42,19 @@
 ;; function u0:0:
 ;; block0:
 ;;   mov w13, w0
-;;   movn w12, #65531
+;;   movn w14, #65531
-;;   adds x14, x13, x12
+;;   adds x13, x13, x14
 ;;   b.hs #trap=heap_oob
-;;   ldr x15, [x2, #8]
+;;   ldr x14, [x2, #8]
-;;   ldr x2, [x2]
+;;   ldr x15, [x2]
-;;   add x0, x2, x0, UXTW
+;;   add x15, x15, x0, UXTW
-;;   movz x13, #65535, LSL #16
+;;   movz x0, #65535, LSL #16
-;;   add x0, x0, x13
+;;   add x15, x15, x0
-;;   movz x13, #0
+;;   movz x0, #0
-;;   subs xzr, x14, x15
+;;   subs xzr, x13, x14
-;;   csel x0, x13, x0, hi
+;;   csel x15, x0, x15, hi
 ;;   csdb
-;;   str w1, [x0]
+;;   str w1, [x15]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -62,19 +62,19 @@
 ;; function u0:1:
 ;; block0:
 ;;   mov w13, w0
-;;   movn w12, #65531
+;;   movn w14, #65531
-;;   adds x14, x13, x12
+;;   adds x13, x13, x14
 ;;   b.hs #trap=heap_oob
-;;   ldr x15, [x1, #8]
+;;   ldr x14, [x1, #8]
-;;   ldr x1, [x1]
+;;   ldr x15, [x1]
-;;   add x0, x1, x0, UXTW
+;;   add x15, x15, x0, UXTW
-;;   movz x13, #65535, LSL #16
+;;   movz x0, #65535, LSL #16
-;;   add x0, x0, x13
+;;   add x15, x15, x0
-;;   movz x13, #0
+;;   movz x0, #0
-;;   subs xzr, x14, x15
+;;   subs xzr, x13, x14
-;;   csel x0, x13, x0, hi
+;;   csel x15, x0, x15, hi
 ;;   csdb
-;;   ldr w0, [x0]
+;;   ldr w0, [x15]
 ;;   b label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat

@@ -45,11 +45,11 @@
 ;;   ldr x10, [x2, #8]
 ;;   ldr x11, [x2]
 ;;   add x11, x11, x0, UXTW
-;;   movz x8, #0
+;;   movz x12, #0
 ;;   subs xzr, x9, x10
-;;   csel x11, x8, x11, hs
+;;   csel x10, x12, x11, hs
 ;;   csdb
-;;   strb w1, [x11]
+;;   strb w1, [x10]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -60,11 +60,11 @@
 ;;   ldr x10, [x1, #8]
 ;;   ldr x11, [x1]
 ;;   add x11, x11, x0, UXTW
-;;   movz x8, #0
+;;   movz x12, #0
 ;;   subs xzr, x9, x10
-;;   csel x11, x8, x11, hs
+;;   csel x10, x12, x11, hs
 ;;   csdb
-;;   ldrb w0, [x11]
+;;   ldrb w0, [x10]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat

@@ -43,16 +43,16 @@
 ;; block0:
 ;;   mov w12, w0
 ;;   ldr x13, [x2, #8]
-;;   movn x11, #4096
+;;   movn x14, #4096
-;;   add x13, x13, x11
+;;   add x13, x13, x14
 ;;   ldr x14, [x2]
 ;;   add x14, x14, x0, UXTW
 ;;   add x14, x14, #4096
-;;   movz x11, #0
+;;   movz x15, #0
 ;;   subs xzr, x12, x13
-;;   csel x14, x11, x14, hi
+;;   csel x13, x15, x14, hi
 ;;   csdb
-;;   strb w1, [x14]
+;;   strb w1, [x13]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -61,16 +61,16 @@
 ;; block0:
 ;;   mov w12, w0
 ;;   ldr x13, [x1, #8]
-;;   movn x11, #4096
+;;   movn x14, #4096
-;;   add x13, x13, x11
+;;   add x13, x13, x14
 ;;   ldr x14, [x1]
 ;;   add x14, x14, x0, UXTW
 ;;   add x14, x14, #4096
-;;   movz x11, #0
+;;   movz x15, #0
 ;;   subs xzr, x12, x13
-;;   csel x14, x11, x14, hi
+;;   csel x13, x15, x14, hi
 ;;   csdb
-;;   ldrb w0, [x14]
+;;   ldrb w0, [x13]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i32_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat

@@ -42,19 +42,19 @@
 ;; function u0:0:
 ;; block0:
 ;;   mov w13, w0
-;;   movn w12, #65534
+;;   movn w14, #65534
-;;   adds x14, x13, x12
+;;   adds x13, x13, x14
 ;;   b.hs #trap=heap_oob
-;;   ldr x15, [x2, #8]
+;;   ldr x14, [x2, #8]
-;;   ldr x2, [x2]
+;;   ldr x15, [x2]
-;;   add x0, x2, x0, UXTW
+;;   add x15, x15, x0, UXTW
-;;   movz x13, #65535, LSL #16
+;;   movz x0, #65535, LSL #16
-;;   add x0, x0, x13
+;;   add x15, x15, x0
-;;   movz x13, #0
+;;   movz x0, #0
-;;   subs xzr, x14, x15
+;;   subs xzr, x13, x14
-;;   csel x0, x13, x0, hi
+;;   csel x15, x0, x15, hi
 ;;   csdb
-;;   strb w1, [x0]
+;;   strb w1, [x15]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -62,19 +62,19 @@
 ;; function u0:1:
 ;; block0:
 ;;   mov w13, w0
-;;   movn w12, #65534
+;;   movn w14, #65534
-;;   adds x14, x13, x12
+;;   adds x13, x13, x14
 ;;   b.hs #trap=heap_oob
-;;   ldr x15, [x1, #8]
+;;   ldr x14, [x1, #8]
-;;   ldr x1, [x1]
+;;   ldr x15, [x1]
-;;   add x0, x1, x0, UXTW
+;;   add x15, x15, x0, UXTW
-;;   movz x13, #65535, LSL #16
+;;   movz x0, #65535, LSL #16
-;;   add x0, x0, x13
+;;   add x15, x15, x0
-;;   movz x13, #0
+;;   movz x0, #0
-;;   subs xzr, x14, x15
+;;   subs xzr, x13, x14
-;;   csel x0, x13, x0, hi
+;;   csel x15, x0, x15, hi
 ;;   csdb
-;;   ldrb w0, [x0]
+;;   ldrb w0, [x15]
 ;;   b label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat

@@ -45,11 +45,11 @@
 ;;   ldr x10, [x2, #8]
 ;;   ldr x11, [x2]
 ;;   add x11, x11, x0, UXTW
-;;   movz x8, #0
+;;   movz x12, #0
 ;;   subs xzr, x9, x10
-;;   csel x11, x8, x11, hi
+;;   csel x10, x12, x11, hi
 ;;   csdb
-;;   str w1, [x11]
+;;   str w1, [x10]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -60,11 +60,11 @@
 ;;   ldr x10, [x1, #8]
 ;;   ldr x11, [x1]
 ;;   add x11, x11, x0, UXTW
-;;   movz x8, #0
+;;   movz x12, #0
 ;;   subs xzr, x9, x10
-;;   csel x11, x8, x11, hi
+;;   csel x10, x12, x11, hi
 ;;   csdb
-;;   ldr w0, [x11]
+;;   ldr w0, [x10]
 ;;   b label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat

@@ -46,11 +46,11 @@
 ;;   ldr x12, [x2]
 ;;   add x12, x12, x0, UXTW
 ;;   add x12, x12, #4096
-;;   movz x9, #0
+;;   movz x13, #0
 ;;   subs xzr, x10, x11
-;;   csel x12, x9, x12, hi
+;;   csel x11, x13, x12, hi
 ;;   csdb
-;;   str w1, [x12]
+;;   str w1, [x11]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -62,11 +62,11 @@
 ;;   ldr x12, [x1]
 ;;   add x12, x12, x0, UXTW
 ;;   add x12, x12, #4096
-;;   movz x9, #0
+;;   movz x13, #0
 ;;   subs xzr, x10, x11
-;;   csel x12, x9, x12, hi
+;;   csel x11, x13, x12, hi
 ;;   csdb
-;;   ldr w0, [x12]
+;;   ldr w0, [x11]
 ;;   b label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat

@@ -45,13 +45,13 @@
 ;;   ldr x12, [x2, #8]
 ;;   ldr x13, [x2]
 ;;   add x13, x13, x0, UXTW
-;;   movz x10, #65535, LSL #16
+;;   movz x14, #65535, LSL #16
-;;   add x13, x13, x10
+;;   add x13, x13, x14
-;;   movz x10, #0
+;;   movz x14, #0
 ;;   subs xzr, x11, x12
-;;   csel x13, x10, x13, hi
+;;   csel x12, x14, x13, hi
 ;;   csdb
-;;   str w1, [x13]
+;;   str w1, [x12]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -62,13 +62,13 @@
 ;;   ldr x12, [x1, #8]
 ;;   ldr x13, [x1]
 ;;   add x13, x13, x0, UXTW
-;;   movz x10, #65535, LSL #16
+;;   movz x14, #65535, LSL #16
-;;   add x13, x13, x10
+;;   add x13, x13, x14
-;;   movz x10, #0
+;;   movz x14, #0
 ;;   subs xzr, x11, x12
-;;   csel x13, x10, x13, hi
+;;   csel x12, x14, x13, hi
 ;;   csdb
-;;   ldr w0, [x13]
+;;   ldr w0, [x12]
 ;;   b label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat

@@ -45,11 +45,11 @@
 ;;   ldr x10, [x2, #8]
 ;;   ldr x11, [x2]
 ;;   add x11, x11, x0, UXTW
-;;   movz x8, #0
+;;   movz x12, #0
 ;;   subs xzr, x9, x10
-;;   csel x11, x8, x11, hs
+;;   csel x10, x12, x11, hs
 ;;   csdb
-;;   strb w1, [x11]
+;;   strb w1, [x10]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -60,11 +60,11 @@
 ;;   ldr x10, [x1, #8]
 ;;   ldr x11, [x1]
 ;;   add x11, x11, x0, UXTW
-;;   movz x8, #0
+;;   movz x12, #0
 ;;   subs xzr, x9, x10
-;;   csel x11, x8, x11, hs
+;;   csel x10, x12, x11, hs
 ;;   csdb
-;;   ldrb w0, [x11]
+;;   ldrb w0, [x10]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat

@@ -46,11 +46,11 @@
 ;;   ldr x12, [x2]
 ;;   add x12, x12, x0, UXTW
 ;;   add x12, x12, #4096
-;;   movz x9, #0
+;;   movz x13, #0
 ;;   subs xzr, x10, x11
-;;   csel x12, x9, x12, hi
+;;   csel x11, x13, x12, hi
 ;;   csdb
-;;   strb w1, [x12]
+;;   strb w1, [x11]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -62,11 +62,11 @@
 ;;   ldr x12, [x1]
 ;;   add x12, x12, x0, UXTW
 ;;   add x12, x12, #4096
-;;   movz x9, #0
+;;   movz x13, #0
 ;;   subs xzr, x10, x11
-;;   csel x12, x9, x12, hi
+;;   csel x11, x13, x12, hi
 ;;   csdb
-;;   ldrb w0, [x12]
+;;   ldrb w0, [x11]
 ;;   b label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i32_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat

@@ -45,13 +45,13 @@
 ;;   ldr x12, [x2, #8]
 ;;   ldr x13, [x2]
 ;;   add x13, x13, x0, UXTW
-;;   movz x10, #65535, LSL #16
+;;   movz x14, #65535, LSL #16
-;;   add x13, x13, x10
+;;   add x13, x13, x14
-;;   movz x10, #0
+;;   movz x14, #0
 ;;   subs xzr, x11, x12
-;;   csel x13, x10, x13, hi
+;;   csel x12, x14, x13, hi
 ;;   csdb
-;;   strb w1, [x13]
+;;   strb w1, [x12]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -62,13 +62,13 @@
 ;;   ldr x12, [x1, #8]
 ;;   ldr x13, [x1]
 ;;   add x13, x13, x0, UXTW
-;;   movz x10, #65535, LSL #16
+;;   movz x14, #65535, LSL #16
-;;   add x13, x13, x10
+;;   add x13, x13, x14
-;;   movz x10, #0
+;;   movz x14, #0
 ;;   subs xzr, x11, x12
-;;   csel x13, x10, x13, hi
+;;   csel x12, x14, x13, hi
 ;;   csdb
-;;   ldrb w0, [x13]
+;;   ldrb w0, [x12]
 ;;   b label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0x1000_offset.wat

@@ -42,9 +42,9 @@
 ;; function u0:0:
 ;; block0:
 ;;   ldr x8, [x2, #8]
-;;   movn x7, #4099
+;;   movn x9, #4099
-;;   add x9, x8, x7
+;;   add x8, x8, x9
-;;   subs xzr, x0, x9
+;;   subs xzr, x0, x8
 ;;   b.hi label3 ; b label1
 ;; block1:
 ;;   ldr x10, [x2]
@@ -59,9 +59,9 @@
 ;; function u0:1:
 ;; block0:
 ;;   ldr x8, [x1, #8]
-;;   movn x7, #4099
+;;   movn x9, #4099
-;;   add x9, x8, x7
+;;   add x8, x8, x9
-;;   subs xzr, x0, x9
+;;   subs xzr, x0, x8
 ;;   b.hi label3 ; b label1
 ;; block1:
 ;;   ldr x10, [x1]

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i32_access_0xffff0000_offset.wat

@@ -41,11 +41,11 @@
 
 ;; function u0:0:
 ;; block0:
-;;   movn w8, #65531
+;;   movn w9, #65531
-;;   adds x10, x0, x8
+;;   adds x9, x0, x9
 ;;   b.hs #trap=heap_oob
-;;   ldr x11, [x2, #8]
+;;   ldr x10, [x2, #8]
-;;   subs xzr, x10, x11
+;;   subs xzr, x9, x10
 ;;   b.hi label3 ; b label1
 ;; block1:
 ;;   ldr x12, [x2]
@@ -60,11 +60,11 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   movn w8, #65531
+;;   movn w9, #65531
-;;   adds x10, x0, x8
+;;   adds x9, x0, x9
 ;;   b.hs #trap=heap_oob
-;;   ldr x11, [x1, #8]
+;;   ldr x10, [x1, #8]
-;;   subs xzr, x10, x11
+;;   subs xzr, x9, x10
 ;;   b.hi label3 ; b label1
 ;; block1:
 ;;   ldr x12, [x1]

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0x1000_offset.wat

@@ -42,9 +42,9 @@
 ;; function u0:0:
 ;; block0:
 ;;   ldr x8, [x2, #8]
-;;   movn x7, #4096
+;;   movn x9, #4096
-;;   add x9, x8, x7
+;;   add x8, x8, x9
-;;   subs xzr, x0, x9
+;;   subs xzr, x0, x8
 ;;   b.hi label3 ; b label1
 ;; block1:
 ;;   ldr x10, [x2]
@@ -59,9 +59,9 @@
 ;; function u0:1:
 ;; block0:
 ;;   ldr x8, [x1, #8]
-;;   movn x7, #4096
+;;   movn x9, #4096
-;;   add x9, x8, x7
+;;   add x8, x8, x9
-;;   subs xzr, x0, x9
+;;   subs xzr, x0, x8
 ;;   b.hi label3 ; b label1
 ;; block1:
 ;;   ldr x10, [x1]

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i64_index_0_guard_no_spectre_i8_access_0xffff0000_offset.wat

@@ -41,11 +41,11 @@
 
 ;; function u0:0:
 ;; block0:
-;;   movn w8, #65534
+;;   movn w9, #65534
-;;   adds x10, x0, x8
+;;   adds x9, x0, x9
 ;;   b.hs #trap=heap_oob
-;;   ldr x11, [x2, #8]
+;;   ldr x10, [x2, #8]
-;;   subs xzr, x10, x11
+;;   subs xzr, x9, x10
 ;;   b.hi label3 ; b label1
 ;; block1:
 ;;   ldr x12, [x2]
@@ -60,11 +60,11 @@
 ;;
 ;; function u0:1:
 ;; block0:
-;;   movn w8, #65534
+;;   movn w9, #65534
-;;   adds x10, x0, x8
+;;   adds x9, x0, x9
 ;;   b.hs #trap=heap_oob
-;;   ldr x11, [x1, #8]
+;;   ldr x10, [x1, #8]
-;;   subs xzr, x10, x11
+;;   subs xzr, x9, x10
 ;;   b.hi label3 ; b label1
 ;; block1:
 ;;   ldr x12, [x1]

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat

@@ -45,11 +45,11 @@
 ;;   sub x9, x9, #4
 ;;   ldr x10, [x2]
 ;;   add x10, x10, x0
-;;   movz x8, #0
+;;   movz x11, #0
 ;;   subs xzr, x0, x9
-;;   csel x11, x8, x10, hi
+;;   csel x10, x11, x10, hi
 ;;   csdb
-;;   str w1, [x11]
+;;   str w1, [x10]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -60,11 +60,11 @@
 ;;   sub x9, x9, #4
 ;;   ldr x10, [x1]
 ;;   add x10, x10, x0
-;;   movz x8, #0
+;;   movz x11, #0
 ;;   subs xzr, x0, x9
-;;   csel x11, x8, x10, hi
+;;   csel x10, x11, x10, hi
 ;;   csdb
-;;   ldr w0, [x11]
+;;   ldr w0, [x10]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat

@@ -42,16 +42,16 @@
 ;; function u0:0:
 ;; block0:
 ;;   ldr x11, [x2, #8]
-;;   movn x10, #4099
+;;   movn x12, #4099
-;;   add x12, x11, x10
+;;   add x11, x11, x12
-;;   ldr x11, [x2]
+;;   ldr x12, [x2]
-;;   add x11, x11, x0
+;;   add x12, x12, x0
-;;   add x11, x11, #4096
+;;   add x12, x12, #4096
-;;   movz x10, #0
+;;   movz x13, #0
-;;   subs xzr, x0, x12
+;;   subs xzr, x0, x11
-;;   csel x13, x10, x11, hi
+;;   csel x12, x13, x12, hi
 ;;   csdb
-;;   str w1, [x13]
+;;   str w1, [x12]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -59,16 +59,16 @@
 ;; function u0:1:
 ;; block0:
 ;;   ldr x11, [x1, #8]
-;;   movn x10, #4099
+;;   movn x12, #4099
-;;   add x12, x11, x10
+;;   add x11, x11, x12
-;;   ldr x11, [x1]
+;;   ldr x12, [x1]
-;;   add x11, x11, x0
+;;   add x12, x12, x0
-;;   add x11, x11, #4096
+;;   add x12, x12, #4096
-;;   movz x10, #0
+;;   movz x13, #0
-;;   subs xzr, x0, x12
+;;   subs xzr, x0, x11
-;;   csel x13, x10, x11, hi
+;;   csel x12, x13, x12, hi
 ;;   csdb
-;;   ldr w0, [x13]
+;;   ldr w0, [x12]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i32_access_0xffff0000_offset.wat

@@ -41,38 +41,38 @@
 
 ;; function u0:0:
 ;; block0:
-;;   movn w11, #65531
+;;   movn w12, #65531
-;;   adds x13, x0, x11
+;;   adds x12, x0, x12
 ;;   b.hs #trap=heap_oob
-;;   ldr x14, [x2, #8]
+;;   ldr x13, [x2, #8]
-;;   ldr x15, [x2]
+;;   ldr x14, [x2]
-;;   add x15, x15, x0
+;;   add x14, x14, x0
-;;   movz x12, #65535, LSL #16
+;;   movz x15, #65535, LSL #16
-;;   add x15, x15, x12
+;;   add x14, x14, x15
-;;   movz x12, #0
+;;   movz x15, #0
-;;   subs xzr, x13, x14
+;;   subs xzr, x12, x13
-;;   csel x15, x12, x15, hi
+;;   csel x14, x15, x14, hi
 ;;   csdb
-;;   str w1, [x15]
+;;   str w1, [x14]
 ;;   b label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   movn w11, #65531
+;;   movn w12, #65531
-;;   adds x13, x0, x11
+;;   adds x12, x0, x12
 ;;   b.hs #trap=heap_oob
-;;   ldr x14, [x1, #8]
+;;   ldr x13, [x1, #8]
-;;   ldr x15, [x1]
+;;   ldr x14, [x1]
-;;   add x15, x15, x0
+;;   add x14, x14, x0
-;;   movz x12, #65535, LSL #16
+;;   movz x15, #65535, LSL #16
-;;   add x15, x15, x12
+;;   add x14, x14, x15
-;;   movz x12, #0
+;;   movz x15, #0
-;;   subs xzr, x13, x14
+;;   subs xzr, x12, x13
-;;   csel x15, x12, x15, hi
+;;   csel x14, x15, x14, hi
 ;;   csdb
-;;   ldr w0, [x15]
+;;   ldr w0, [x14]
 ;;   b label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat

@@ -44,11 +44,11 @@
 ;;   ldr x8, [x2, #8]
 ;;   ldr x9, [x2]
 ;;   add x9, x9, x0
-;;   movz x7, #0
+;;   movz x10, #0
 ;;   subs xzr, x0, x8
-;;   csel x10, x7, x9, hs
+;;   csel x9, x10, x9, hs
 ;;   csdb
-;;   strb w1, [x10]
+;;   strb w1, [x9]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -58,11 +58,11 @@
 ;;   ldr x8, [x1, #8]
 ;;   ldr x9, [x1]
 ;;   add x9, x9, x0
-;;   movz x7, #0
+;;   movz x10, #0
 ;;   subs xzr, x0, x8
-;;   csel x10, x7, x9, hs
+;;   csel x9, x10, x9, hs
 ;;   csdb
-;;   ldrb w0, [x10]
+;;   ldrb w0, [x9]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat

@@ -42,16 +42,16 @@
 ;; function u0:0:
 ;; block0:
 ;;   ldr x11, [x2, #8]
-;;   movn x10, #4096
+;;   movn x12, #4096
-;;   add x12, x11, x10
+;;   add x11, x11, x12
-;;   ldr x11, [x2]
+;;   ldr x12, [x2]
-;;   add x11, x11, x0
+;;   add x12, x12, x0
-;;   add x11, x11, #4096
+;;   add x12, x12, #4096
-;;   movz x10, #0
+;;   movz x13, #0
-;;   subs xzr, x0, x12
+;;   subs xzr, x0, x11
-;;   csel x13, x10, x11, hi
+;;   csel x12, x13, x12, hi
 ;;   csdb
-;;   strb w1, [x13]
+;;   strb w1, [x12]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -59,16 +59,16 @@
 ;; function u0:1:
 ;; block0:
 ;;   ldr x11, [x1, #8]
-;;   movn x10, #4096
+;;   movn x12, #4096
-;;   add x12, x11, x10
+;;   add x11, x11, x12
-;;   ldr x11, [x1]
+;;   ldr x12, [x1]
-;;   add x11, x11, x0
+;;   add x12, x12, x0
-;;   add x11, x11, #4096
+;;   add x12, x12, #4096
-;;   movz x10, #0
+;;   movz x13, #0
-;;   subs xzr, x0, x12
+;;   subs xzr, x0, x11
-;;   csel x13, x10, x11, hi
+;;   csel x12, x13, x12, hi
 ;;   csdb
-;;   ldrb w0, [x13]
+;;   ldrb w0, [x12]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i64_index_0_guard_yes_spectre_i8_access_0xffff0000_offset.wat

@@ -41,38 +41,38 @@
 
 ;; function u0:0:
 ;; block0:
-;;   movn w11, #65534
+;;   movn w12, #65534
-;;   adds x13, x0, x11
+;;   adds x12, x0, x12
 ;;   b.hs #trap=heap_oob
-;;   ldr x14, [x2, #8]
+;;   ldr x13, [x2, #8]
-;;   ldr x15, [x2]
+;;   ldr x14, [x2]
-;;   add x15, x15, x0
+;;   add x14, x14, x0
-;;   movz x12, #65535, LSL #16
+;;   movz x15, #65535, LSL #16
-;;   add x15, x15, x12
+;;   add x14, x14, x15
-;;   movz x12, #0
+;;   movz x15, #0
-;;   subs xzr, x13, x14
+;;   subs xzr, x12, x13
-;;   csel x15, x12, x15, hi
+;;   csel x14, x15, x14, hi
 ;;   csdb
-;;   strb w1, [x15]
+;;   strb w1, [x14]
 ;;   b label1
 ;; block1:
 ;;   ret
 ;;
 ;; function u0:1:
 ;; block0:
-;;   movn w11, #65534
+;;   movn w12, #65534
-;;   adds x13, x0, x11
+;;   adds x12, x0, x12
 ;;   b.hs #trap=heap_oob
-;;   ldr x14, [x1, #8]
+;;   ldr x13, [x1, #8]
-;;   ldr x15, [x1]
+;;   ldr x14, [x1]
-;;   add x15, x15, x0
+;;   add x14, x14, x0
-;;   movz x12, #65535, LSL #16
+;;   movz x15, #65535, LSL #16
-;;   add x15, x15, x12
+;;   add x14, x14, x15
-;;   movz x12, #0
+;;   movz x15, #0
-;;   subs xzr, x13, x14
+;;   subs xzr, x12, x13
-;;   csel x15, x12, x15, hi
+;;   csel x14, x15, x14, hi
 ;;   csdb
-;;   ldrb w0, [x15]
+;;   ldrb w0, [x14]
 ;;   b label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat

@@ -44,11 +44,11 @@
 ;;   ldr x8, [x2, #8]
 ;;   ldr x9, [x2]
 ;;   add x9, x9, x0
-;;   movz x7, #0
+;;   movz x10, #0
 ;;   subs xzr, x0, x8
-;;   csel x10, x7, x9, hi
+;;   csel x9, x10, x9, hi
 ;;   csdb
-;;   str w1, [x10]
+;;   str w1, [x9]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -58,11 +58,11 @@
 ;;   ldr x8, [x1, #8]
 ;;   ldr x9, [x1]
 ;;   add x9, x9, x0
-;;   movz x7, #0
+;;   movz x10, #0
 ;;   subs xzr, x0, x8
-;;   csel x10, x7, x9, hi
+;;   csel x9, x10, x9, hi
 ;;   csdb
-;;   ldr w0, [x10]
+;;   ldr w0, [x9]
 ;;   b label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat

@@ -45,11 +45,11 @@
 ;;   ldr x10, [x2]
 ;;   add x10, x10, x0
 ;;   add x10, x10, #4096
-;;   movz x8, #0
+;;   movz x11, #0
 ;;   subs xzr, x0, x9
-;;   csel x11, x8, x10, hi
+;;   csel x10, x11, x10, hi
 ;;   csdb
-;;   str w1, [x11]
+;;   str w1, [x10]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -60,11 +60,11 @@
 ;;   ldr x10, [x1]
 ;;   add x10, x10, x0
 ;;   add x10, x10, #4096
-;;   movz x8, #0
+;;   movz x11, #0
 ;;   subs xzr, x0, x9
-;;   csel x11, x8, x10, hi
+;;   csel x10, x11, x10, hi
 ;;   csdb
-;;   ldr w0, [x11]
+;;   ldr w0, [x10]
 ;;   b label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0xffff0000_offset.wat

@@ -44,13 +44,13 @@
 ;;   ldr x10, [x2, #8]
 ;;   ldr x11, [x2]
 ;;   add x11, x11, x0
-;;   movz x9, #65535, LSL #16
+;;   movz x12, #65535, LSL #16
-;;   add x11, x11, x9
+;;   add x11, x11, x12
-;;   movz x9, #0
+;;   movz x12, #0
 ;;   subs xzr, x0, x10
-;;   csel x12, x9, x11, hi
+;;   csel x11, x12, x11, hi
 ;;   csdb
-;;   str w1, [x12]
+;;   str w1, [x11]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -60,13 +60,13 @@
 ;;   ldr x10, [x1, #8]
 ;;   ldr x11, [x1]
 ;;   add x11, x11, x0
-;;   movz x9, #65535, LSL #16
+;;   movz x12, #65535, LSL #16
-;;   add x11, x11, x9
+;;   add x11, x11, x12
-;;   movz x9, #0
+;;   movz x12, #0
 ;;   subs xzr, x0, x10
-;;   csel x12, x9, x11, hi
+;;   csel x11, x12, x11, hi
 ;;   csdb
-;;   ldr w0, [x12]
+;;   ldr w0, [x11]
 ;;   b label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat

@@ -44,11 +44,11 @@
 ;;   ldr x8, [x2, #8]
 ;;   ldr x9, [x2]
 ;;   add x9, x9, x0
-;;   movz x7, #0
+;;   movz x10, #0
 ;;   subs xzr, x0, x8
-;;   csel x10, x7, x9, hs
+;;   csel x9, x10, x9, hs
 ;;   csdb
-;;   strb w1, [x10]
+;;   strb w1, [x9]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -58,11 +58,11 @@
 ;;   ldr x8, [x1, #8]
 ;;   ldr x9, [x1]
 ;;   add x9, x9, x0
-;;   movz x7, #0
+;;   movz x10, #0
 ;;   subs xzr, x0, x8
-;;   csel x10, x7, x9, hs
+;;   csel x9, x10, x9, hs
 ;;   csdb
-;;   ldrb w0, [x10]
+;;   ldrb w0, [x9]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat

@@ -45,11 +45,11 @@
 ;;   ldr x10, [x2]
 ;;   add x10, x10, x0
 ;;   add x10, x10, #4096
-;;   movz x8, #0
+;;   movz x11, #0
 ;;   subs xzr, x0, x9
-;;   csel x11, x8, x10, hi
+;;   csel x10, x11, x10, hi
 ;;   csdb
-;;   strb w1, [x11]
+;;   strb w1, [x10]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -60,11 +60,11 @@
 ;;   ldr x10, [x1]
 ;;   add x10, x10, x0
 ;;   add x10, x10, #4096
-;;   movz x8, #0
+;;   movz x11, #0
 ;;   subs xzr, x0, x9
-;;   csel x11, x8, x10, hi
+;;   csel x10, x11, x10, hi
 ;;   csdb
-;;   ldrb w0, [x11]
+;;   ldrb w0, [x10]
 ;;   b label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_dynamic_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0xffff0000_offset.wat

@@ -44,13 +44,13 @@
 ;;   ldr x10, [x2, #8]
 ;;   ldr x11, [x2]
 ;;   add x11, x11, x0
-;;   movz x9, #65535, LSL #16
+;;   movz x12, #65535, LSL #16
-;;   add x11, x11, x9
+;;   add x11, x11, x12
-;;   movz x9, #0
+;;   movz x12, #0
 ;;   subs xzr, x0, x10
-;;   csel x12, x9, x11, hi
+;;   csel x11, x12, x11, hi
 ;;   csdb
-;;   strb w1, [x12]
+;;   strb w1, [x11]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -60,13 +60,13 @@
 ;;   ldr x10, [x1, #8]
 ;;   ldr x11, [x1]
 ;;   add x11, x11, x0
-;;   movz x9, #65535, LSL #16
+;;   movz x12, #65535, LSL #16
-;;   add x11, x11, x9
+;;   add x11, x11, x12
-;;   movz x9, #0
+;;   movz x12, #0
 ;;   subs xzr, x0, x10
-;;   csel x12, x9, x11, hi
+;;   csel x11, x12, x11, hi
 ;;   csdb
-;;   ldrb w0, [x12]
+;;   ldrb w0, [x11]
 ;;   b label1
 ;; block1:
 ;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0_offset.wat

@@ -42,12 +42,12 @@
 ;;   mov w9, w0
 ;;   ldr x10, [x2]
 ;;   add x10, x10, x0, UXTW
-;;   orr x7, xzr, #268435452
 ;;   movz x11, #0
-;;   subs xzr, x9, x7
+;;   orr x8, xzr, #268435452
-;;   csel x12, x11, x10, hi
+;;   subs xzr, x9, x8
+;;   csel x11, x11, x10, hi
 ;;   csdb
-;;   str w1, [x12]
+;;   str w1, [x11]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -57,12 +57,12 @@
 ;;   mov w9, w0
 ;;   ldr x10, [x1]
 ;;   add x10, x10, x0, UXTW
-;;   orr x7, xzr, #268435452
 ;;   movz x11, #0
-;;   subs xzr, x9, x7
+;;   orr x8, xzr, #268435452
-;;   csel x12, x11, x10, hi
+;;   subs xzr, x9, x8
+;;   csel x11, x11, x10, hi
 ;;   csdb
-;;   ldr w0, [x12]
+;;   ldr w0, [x11]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat

@@ -43,13 +43,13 @@
 ;;   ldr x12, [x2]
 ;;   add x12, x12, x0, UXTW
 ;;   add x12, x12, #4096
-;;   movz w9, #61436
-;;   movk w9, w9, #4095, LSL #16
 ;;   movz x13, #0
-;;   subs xzr, x11, x9
+;;   movz w10, #61436
-;;   csel x15, x13, x12, hi
+;;   movk w10, w10, #4095, LSL #16
+;;   subs xzr, x11, x10
+;;   csel x14, x13, x12, hi
 ;;   csdb
-;;   str w1, [x15]
+;;   str w1, [x14]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -60,13 +60,13 @@
 ;;   ldr x12, [x1]
 ;;   add x12, x12, x0, UXTW
 ;;   add x12, x12, #4096
-;;   movz w9, #61436
-;;   movk w9, w9, #4095, LSL #16
 ;;   movz x13, #0
-;;   subs xzr, x11, x9
+;;   movz w10, #61436
-;;   csel x15, x13, x12, hi
+;;   movk w10, w10, #4095, LSL #16
+;;   subs xzr, x11, x10
+;;   csel x14, x13, x12, hi
 ;;   csdb
-;;   ldr w0, [x15]
+;;   ldr w0, [x14]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0_offset.wat

@@ -42,12 +42,12 @@
 ;;   mov w9, w0
 ;;   ldr x10, [x2]
 ;;   add x10, x10, x0, UXTW
-;;   orr x7, xzr, #268435455
 ;;   movz x11, #0
-;;   subs xzr, x9, x7
+;;   orr x8, xzr, #268435455
-;;   csel x12, x11, x10, hi
+;;   subs xzr, x9, x8
+;;   csel x11, x11, x10, hi
 ;;   csdb
-;;   strb w1, [x12]
+;;   strb w1, [x11]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -57,12 +57,12 @@
 ;;   mov w9, w0
 ;;   ldr x10, [x1]
 ;;   add x10, x10, x0, UXTW
-;;   orr x7, xzr, #268435455
 ;;   movz x11, #0
-;;   subs xzr, x9, x7
+;;   orr x8, xzr, #268435455
-;;   csel x12, x11, x10, hi
+;;   subs xzr, x9, x8
+;;   csel x11, x11, x10, hi
 ;;   csdb
-;;   ldrb w0, [x12]
+;;   ldrb w0, [x11]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_static_kind_i32_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat

@@ -43,13 +43,13 @@
 ;;   ldr x12, [x2]
 ;;   add x12, x12, x0, UXTW
 ;;   add x12, x12, #4096
-;;   movz w9, #61439
-;;   movk w9, w9, #4095, LSL #16
 ;;   movz x13, #0
-;;   subs xzr, x11, x9
+;;   movz w10, #61439
-;;   csel x15, x13, x12, hi
+;;   movk w10, w10, #4095, LSL #16
+;;   subs xzr, x11, x10
+;;   csel x14, x13, x12, hi
 ;;   csdb
-;;   strb w1, [x15]
+;;   strb w1, [x14]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -60,13 +60,13 @@
 ;;   ldr x12, [x1]
 ;;   add x12, x12, x0, UXTW
 ;;   add x12, x12, #4096
-;;   movz w9, #61439
-;;   movk w9, w9, #4095, LSL #16
 ;;   movz x13, #0
-;;   subs xzr, x11, x9
+;;   movz w10, #61439
-;;   csel x15, x13, x12, hi
+;;   movk w10, w10, #4095, LSL #16
+;;   subs xzr, x11, x10
+;;   csel x14, x13, x12, hi
 ;;   csdb
-;;   ldrb w0, [x15]
+;;   ldrb w0, [x14]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0_offset.wat

@@ -41,12 +41,12 @@
 ;; block0:
 ;;   ldr x8, [x2]
 ;;   add x8, x8, x0
-;;   orr x6, xzr, #268435452
 ;;   movz x9, #0
-;;   subs xzr, x0, x6
+;;   orr x7, xzr, #268435452
-;;   csel x11, x9, x8, hi
+;;   subs xzr, x0, x7
+;;   csel x10, x9, x8, hi
 ;;   csdb
-;;   str w1, [x11]
+;;   str w1, [x10]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -55,12 +55,12 @@
 ;; block0:
 ;;   ldr x8, [x1]
 ;;   add x8, x8, x0
-;;   orr x6, xzr, #268435452
 ;;   movz x9, #0
-;;   subs xzr, x0, x6
+;;   orr x7, xzr, #268435452
-;;   csel x11, x9, x8, hi
+;;   subs xzr, x0, x7
+;;   csel x10, x9, x8, hi
 ;;   csdb
-;;   ldr w0, [x11]
+;;   ldr w0, [x10]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i32_access_0x1000_offset.wat

@@ -42,13 +42,13 @@
 ;;   ldr x10, [x2]
 ;;   add x10, x10, x0
 ;;   add x10, x10, #4096
-;;   movz w8, #61436
-;;   movk w8, w8, #4095, LSL #16
 ;;   movz x11, #0
-;;   subs xzr, x0, x8
+;;   movz w9, #61436
-;;   csel x14, x11, x10, hi
+;;   movk w9, w9, #4095, LSL #16
+;;   subs xzr, x0, x9
+;;   csel x13, x11, x10, hi
 ;;   csdb
-;;   str w1, [x14]
+;;   str w1, [x13]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -58,13 +58,13 @@
 ;;   ldr x10, [x1]
 ;;   add x10, x10, x0
 ;;   add x10, x10, #4096
-;;   movz w8, #61436
-;;   movk w8, w8, #4095, LSL #16
 ;;   movz x11, #0
-;;   subs xzr, x0, x8
+;;   movz w9, #61436
-;;   csel x14, x11, x10, hi
+;;   movk w9, w9, #4095, LSL #16
+;;   subs xzr, x0, x9
+;;   csel x13, x11, x10, hi
 ;;   csdb
-;;   ldr w0, [x14]
+;;   ldr w0, [x13]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0_offset.wat

@@ -41,12 +41,12 @@
 ;; block0:
 ;;   ldr x8, [x2]
 ;;   add x8, x8, x0
-;;   orr x6, xzr, #268435455
 ;;   movz x9, #0
-;;   subs xzr, x0, x6
+;;   orr x7, xzr, #268435455
-;;   csel x11, x9, x8, hi
+;;   subs xzr, x0, x7
+;;   csel x10, x9, x8, hi
 ;;   csdb
-;;   strb w1, [x11]
+;;   strb w1, [x10]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -55,12 +55,12 @@
 ;; block0:
 ;;   ldr x8, [x1]
 ;;   add x8, x8, x0
-;;   orr x6, xzr, #268435455
 ;;   movz x9, #0
-;;   subs xzr, x0, x6
+;;   orr x7, xzr, #268435455
-;;   csel x11, x9, x8, hi
+;;   subs xzr, x0, x7
+;;   csel x10, x9, x8, hi
 ;;   csdb
-;;   ldrb w0, [x11]
+;;   ldrb w0, [x10]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_static_kind_i64_index_0_guard_yes_spectre_i8_access_0x1000_offset.wat

@@ -42,13 +42,13 @@
 ;;   ldr x10, [x2]
 ;;   add x10, x10, x0
 ;;   add x10, x10, #4096
-;;   movz w8, #61439
-;;   movk w8, w8, #4095, LSL #16
 ;;   movz x11, #0
-;;   subs xzr, x0, x8
+;;   movz w9, #61439
-;;   csel x14, x11, x10, hi
+;;   movk w9, w9, #4095, LSL #16
+;;   subs xzr, x0, x9
+;;   csel x13, x11, x10, hi
 ;;   csdb
-;;   strb w1, [x14]
+;;   strb w1, [x13]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -58,13 +58,13 @@
 ;;   ldr x10, [x1]
 ;;   add x10, x10, x0
 ;;   add x10, x10, #4096
-;;   movz w8, #61439
-;;   movk w8, w8, #4095, LSL #16
 ;;   movz x11, #0
-;;   subs xzr, x0, x8
+;;   movz w9, #61439
-;;   csel x14, x11, x10, hi
+;;   movk w9, w9, #4095, LSL #16
+;;   subs xzr, x0, x9
+;;   csel x13, x11, x10, hi
 ;;   csdb
-;;   ldrb w0, [x14]
+;;   ldrb w0, [x13]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0_offset.wat

@@ -41,12 +41,12 @@
 ;; block0:
 ;;   ldr x8, [x2]
 ;;   add x8, x8, x0
-;;   orr x6, xzr, #268435452
 ;;   movz x9, #0
-;;   subs xzr, x0, x6
+;;   orr x7, xzr, #268435452
-;;   csel x11, x9, x8, hi
+;;   subs xzr, x0, x7
+;;   csel x10, x9, x8, hi
 ;;   csdb
-;;   str w1, [x11]
+;;   str w1, [x10]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -55,12 +55,12 @@
 ;; block0:
 ;;   ldr x8, [x1]
 ;;   add x8, x8, x0
-;;   orr x6, xzr, #268435452
 ;;   movz x9, #0
-;;   subs xzr, x0, x6
+;;   orr x7, xzr, #268435452
-;;   csel x11, x9, x8, hi
+;;   subs xzr, x0, x7
+;;   csel x10, x9, x8, hi
 ;;   csdb
-;;   ldr w0, [x11]
+;;   ldr w0, [x10]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i32_access_0x1000_offset.wat

@@ -42,13 +42,13 @@
 ;;   ldr x10, [x2]
 ;;   add x10, x10, x0
 ;;   add x10, x10, #4096
-;;   movz w8, #61436
-;;   movk w8, w8, #4095, LSL #16
 ;;   movz x11, #0
-;;   subs xzr, x0, x8
+;;   movz w9, #61436
-;;   csel x14, x11, x10, hi
+;;   movk w9, w9, #4095, LSL #16
+;;   subs xzr, x0, x9
+;;   csel x13, x11, x10, hi
 ;;   csdb
-;;   str w1, [x14]
+;;   str w1, [x13]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -58,13 +58,13 @@
 ;;   ldr x10, [x1]
 ;;   add x10, x10, x0
 ;;   add x10, x10, #4096
-;;   movz w8, #61436
-;;   movk w8, w8, #4095, LSL #16
 ;;   movz x11, #0
-;;   subs xzr, x0, x8
+;;   movz w9, #61436
-;;   csel x14, x11, x10, hi
+;;   movk w9, w9, #4095, LSL #16
+;;   subs xzr, x0, x9
+;;   csel x13, x11, x10, hi
 ;;   csdb
-;;   ldr w0, [x14]
+;;   ldr w0, [x13]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0_offset.wat

@@ -41,12 +41,12 @@
 ;; block0:
 ;;   ldr x8, [x2]
 ;;   add x8, x8, x0
-;;   orr x6, xzr, #268435455
 ;;   movz x9, #0
-;;   subs xzr, x0, x6
+;;   orr x7, xzr, #268435455
-;;   csel x11, x9, x8, hi
+;;   subs xzr, x0, x7
+;;   csel x10, x9, x8, hi
 ;;   csdb
-;;   strb w1, [x11]
+;;   strb w1, [x10]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -55,12 +55,12 @@
 ;; block0:
 ;;   ldr x8, [x1]
 ;;   add x8, x8, x0
-;;   orr x6, xzr, #268435455
 ;;   movz x9, #0
-;;   subs xzr, x0, x6
+;;   orr x7, xzr, #268435455
-;;   csel x11, x9, x8, hi
+;;   subs xzr, x0, x7
+;;   csel x10, x9, x8, hi
 ;;   csdb
-;;   ldrb w0, [x11]
+;;   ldrb w0, [x10]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/aarch64/wasm/load_store_static_kind_i64_index_0xffffffff_guard_yes_spectre_i8_access_0x1000_offset.wat

@@ -42,13 +42,13 @@
 ;;   ldr x10, [x2]
 ;;   add x10, x10, x0
 ;;   add x10, x10, #4096
-;;   movz w8, #61439
-;;   movk w8, w8, #4095, LSL #16
 ;;   movz x11, #0
-;;   subs xzr, x0, x8
+;;   movz w9, #61439
-;;   csel x14, x11, x10, hi
+;;   movk w9, w9, #4095, LSL #16
+;;   subs xzr, x0, x9
+;;   csel x13, x11, x10, hi
 ;;   csdb
-;;   strb w1, [x14]
+;;   strb w1, [x13]
 ;;   b label1
 ;; block1:
 ;;   ret
@@ -58,13 +58,13 @@
 ;;   ldr x10, [x1]
 ;;   add x10, x10, x0
 ;;   add x10, x10, #4096
-;;   movz w8, #61439
-;;   movk w8, w8, #4095, LSL #16
 ;;   movz x11, #0
-;;   subs xzr, x0, x8
+;;   movz w9, #61439
-;;   csel x14, x11, x10, hi
+;;   movk w9, w9, #4095, LSL #16
+;;   subs xzr, x0, x9
+;;   csel x13, x11, x10, hi
 ;;   csdb
-;;   ldrb w0, [x14]
+;;   ldrb w0, [x13]
 ;;   b label1
 ;; block1:
-;;   ret
+;;   ret

cranelift/filetests/filetests/isa/riscv64/amodes.clif

@@ -142,22 +142,22 @@ block0(v0: i64, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   add a6,a0,a1
+;   lui a6,1
-;   add a6,a6,a2
+;   addi a6,a6,4
-;   lui a5,1
+;   add a7,a0,a1
-;   addi a5,a5,4
+;   add a7,a7,a2
-;   add t3,a6,a5
+;   add a6,a7,a6
-;   lw a0,0(t3)
+;   lw a0,0(a6)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   add a6, a0, a1
+;   lui a6, 1
-;   add a6, a6, a2
+;   addi a6, a6, 4
-;   lui a5, 1
+;   add a7, a0, a1
-;   addi a5, a5, 4
+;   add a7, a7, a2
-;   add t3, a6, a5
+;   add a6, a7, a6
-;   lw a0, 0(t3)
+;   lw a0, 0(a6)
 ;   ret
 
 function %f10() -> i32 {
@@ -169,14 +169,14 @@ block0:
 
 ; VCode:
 ; block0:
-;   li t0,1234
+;   li t1,1234
-;   lw a0,0(t0)
+;   lw a0,0(t1)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t0, zero, 0x4d2
+;   addi t1, zero, 0x4d2
-;   lw a0, 0(t0)
+;   lw a0, 0(t1)
 ;   ret
 
 function %f11(i64) -> i32 {
@@ -190,15 +190,15 @@ block0(v0: i64):
 ; VCode:
 ; block0:
 ;   lui a1,2048
-;   add a2,a0,a1
+;   add a1,a0,a1
-;   lw a0,0(a2)
+;   lw a0,0(a1)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   lui a1, 0x800
-;   add a2, a0, a1
+;   add a1, a0, a1
-;   lw a0, 0(a2)
+;   lw a0, 0(a1)
 ;   ret
 
 function %f12(i64) -> i32 {
@@ -231,18 +231,18 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   lui a1,244141
+;   lui a2,244141
-;   addi a1,a1,2560
+;   addi a2,a2,2560
-;   add a4,a0,a1
+;   add a2,a0,a2
-;   lw a0,0(a4)
+;   lw a0,0(a2)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   lui a1, 0x3b9ad
+;   lui a2, 0x3b9ad
-;   addi a1, a1, -0x600
+;   addi a2, a2, -0x600
-;   add a4, a0, a1
+;   add a2, a0, a2
-;   lw a0, 0(a4)
+;   lw a0, 0(a2)
 ;   ret
 
 function %f14(i32) -> i32 {
@@ -299,20 +299,20 @@ block0(v0: i64, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   lui a3,1048575
+;   lui a5,1048575
-;   addi a3,a3,4094
+;   addi a5,a5,4094
-;   slli a6,a3,32
+;   slli a4,a5,32
-;   srli t3,a6,32
+;   srli a6,a4,32
-;   lh a0,0(t3)
+;   lh a0,0(a6)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   lui a3, 0xfffff
+;   lui a5, 0xfffff
-;   addi a3, a3, -2
+;   addi a5, a5, -2
-;   slli a6, a3, 0x20
+;   slli a4, a5, 0x20
-;   srli t3, a6, 0x20
+;   srli a6, a4, 0x20
-;   lh a0, 0(t3)
+;   lh a0, 0(a6)
 ;   ret
 
 function %f19(i64, i64, i64) -> i32 {
@@ -325,20 +325,20 @@ block0(v0: i64, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   lui a3,1
+;   lui a5,1
-;   addi a3,a3,2
+;   addi a5,a5,2
-;   slli a6,a3,32
+;   slli a4,a5,32
-;   srli t3,a6,32
+;   srli a6,a4,32
-;   lh a0,0(t3)
+;   lh a0,0(a6)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   lui a3, 1
+;   lui a5, 1
-;   addi a3, a3, 2
+;   addi a5, a5, 2
-;   slli a6, a3, 0x20
+;   slli a4, a5, 0x20
-;   srli t3, a6, 0x20
+;   srli a6, a4, 0x20
-;   lh a0, 0(t3)
+;   lh a0, 0(a6)
 ;   ret
 
 function %f20(i64, i64, i64) -> i32 {
@@ -351,18 +351,18 @@ block0(v0: i64, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   lui a3,1048575
+;   lui a4,1048575
-;   addi a3,a3,4094
+;   addi a4,a4,4094
-;   sext.w a6,a3
+;   sext.w a4,a4
-;   lh a0,0(a6)
+;   lh a0,0(a4)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   lui a3, 0xfffff
+;   lui a4, 0xfffff
-;   addi a3, a3, -2
+;   addi a4, a4, -2
-;   sext.w a6, a3
+;   sext.w a4, a4
-;   lh a0, 0(a6)
+;   lh a0, 0(a4)
 ;   ret
 
 function %f21(i64, i64, i64) -> i32 {
@@ -375,18 +375,18 @@ block0(v0: i64, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   lui a3,1
+;   lui a4,1
-;   addi a3,a3,2
+;   addi a4,a4,2
-;   sext.w a6,a3
+;   sext.w a4,a4
-;   lh a0,0(a6)
+;   lh a0,0(a4)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   lui a3, 1
+;   lui a4, 1
-;   addi a3, a3, 2
+;   addi a4, a4, 2
-;   sext.w a6, a3
+;   sext.w a4, a4
-;   lh a0, 0(a6)
+;   lh a0, 0(a4)
 ;   ret
 
 function %i128(i64) -> i128 {

cranelift/filetests/filetests/isa/riscv64/arithmetic.clif

@@ -131,42 +131,38 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   li t2,2
+;   li a6,2
 ;   li a1,-1
-;   li a3,1
+;   li a2,1
-;   slli a5,a3,63
+;   slli a4,a2,63
-;   eq a7,a1,t2##ty=i64
+;   eq a7,a1,a6##ty=i64
-;   eq t4,a5,a0##ty=i64
+;   eq t3,a4,a0##ty=i64
-;   and t1,a7,t4
+;   and t0,a7,t3
-;   trap_if t1,int_ovf
+;   trap_if t0,int_ovf
-;   li a1,2
+;   trap_ifc int_divz##(zero eq a6)
-;   trap_ifc int_divz##(zero eq a1)
+;   div a0,a0,a6
-;   li a4,2
-;   div a0,a0,a4
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t2, zero, 2
+;   addi a6, zero, 2
 ;   addi a1, zero, -1
-;   addi a3, zero, 1
+;   addi a2, zero, 1
-;   slli a5, a3, 0x3f
+;   slli a4, a2, 0x3f
-;   bne a1, t2, 0xc
+;   bne a1, a6, 0xc
 ;   addi a7, zero, 1
 ;   j 8
 ;   mv a7, zero
-;   bne a5, a0, 0xc
+;   bne a4, a0, 0xc
-;   addi t4, zero, 1
+;   addi t3, zero, 1
 ;   j 8
-;   mv t4, zero
+;   mv t3, zero
-;   and t1, a7, t4
+;   and t0, a7, t3
-;   beqz t1, 8
+;   beqz t0, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
-;   addi a1, zero, 2
+;   bne zero, a6, 8
-;   bne zero, a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
-;   addi a4, zero, 2
+;   div a0, a0, a6
-;   div a0, a0, a4
 ;   ret
 
 function %f8(i64, i64) -> i64 {
@@ -197,19 +193,17 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   li t2,2
+;   li a1,2
-;   trap_ifc int_divz##(zero eq t2)
+;   trap_ifc int_divz##(zero eq a1)
-;   li a2,2
+;   divu a0,a0,a1
-;   divu a0,a0,a2
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t2, zero, 2
+;   addi a1, zero, 2
-;   bne zero, t2, 8
+;   bne zero, a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
-;   addi a2, zero, 2
+;   divu a0, a0, a1
-;   divu a0, a0, a2
 ;   ret
 
 function %f10(i64, i64) -> i64 {
@@ -305,44 +299,44 @@ block0(v0: i32):
 
 ; VCode:
 ; block0:
-;   sext.w t2,a0
+;   li t4,2
-;   li a1,2
+;   sext.w a0,a0
-;   sext.w a3,a1
+;   sext.w a2,t4
-;   li a5,-1
+;   li a4,-1
-;   li a7,1
+;   li a6,1
-;   slli t4,a7,63
+;   slli t3,a6,63
-;   slli t1,t2,32
+;   slli t0,a0,32
-;   eq a0,a5,a3##ty=i32
+;   eq t2,a4,a2##ty=i32
-;   eq a2,t4,t1##ty=i32
+;   eq a1,t3,t0##ty=i32
-;   and a4,a0,a2
+;   and a3,t2,a1
-;   trap_if a4,int_ovf
+;   trap_if a3,int_ovf
-;   trap_ifc int_divz##(zero eq a3)
+;   trap_ifc int_divz##(zero eq a2)
-;   divw a0,t2,a3
+;   divw a0,a0,a2
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   sext.w t2, a0
+;   addi t4, zero, 2
-;   addi a1, zero, 2
+;   sext.w a0, a0
-;   sext.w a3, a1
+;   sext.w a2, t4
-;   addi a5, zero, -1
+;   addi a4, zero, -1
-;   addi a7, zero, 1
+;   addi a6, zero, 1
-;   slli t4, a7, 0x3f
+;   slli t3, a6, 0x3f
-;   slli t1, t2, 0x20
+;   slli t0, a0, 0x20
-;   bne a5, a3, 0xc
+;   bne a4, a2, 0xc
-;   addi a0, zero, 1
+;   addi t2, zero, 1
 ;   j 8
-;   mv a0, zero
+;   mv t2, zero
-;   bne t4, t1, 0xc
+;   bne t3, t0, 0xc
-;   addi a2, zero, 1
+;   addi a1, zero, 1
 ;   j 8
-;   mv a2, zero
+;   mv a1, zero
-;   and a4, a0, a2
+;   and a3, t2, a1
-;   beqz a4, 8
+;   beqz a3, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
-;   bne zero, a3, 8
+;   bne zero, a2, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
-;   divw a0, t2, a3
+;   divw a0, a0, a2
 ;   ret
 
 function %f14(i32, i32) -> i32 {
@@ -381,25 +375,25 @@ block0(v0: i32):
 
 ; VCode:
 ; block0:
-;   li t2,2
+;   li a4,2
-;   slli a1,t2,32
+;   slli a1,a4,32
-;   srli a3,a1,32
+;   srli a2,a1,32
-;   trap_ifc int_divz##(zero eq a3)
+;   trap_ifc int_divz##(zero eq a2)
-;   slli a6,a0,32
+;   slli a5,a0,32
-;   srli t3,a6,32
+;   srli a7,a5,32
-;   divuw a0,t3,a3
+;   divuw a0,a7,a2
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t2, zero, 2
+;   addi a4, zero, 2
-;   slli a1, t2, 0x20
+;   slli a1, a4, 0x20
-;   srli a3, a1, 0x20
+;   srli a2, a1, 0x20
-;   bne zero, a3, 8
+;   bne zero, a2, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
-;   slli a6, a0, 0x20
+;   slli a5, a0, 0x20
-;   srli t3, a6, 0x20
+;   srli a7, a5, 0x20
-;   divuw a0, t3, a3
+;   divuw a0, a7, a2
 ;   ret
 
 function %f16(i32, i32) -> i32 {
@@ -610,14 +604,14 @@ block0(v0: i32):
 
 ; VCode:
 ; block0:
-;   li t2,-1
+;   li a1,-1
-;   subw a0,a0,t2
+;   subw a0,a0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t2, zero, -1
+;   addi a1, zero, -1
-;   subw a0, a0, t2
+;   subw a0, a0, a1
 ;   ret
 
 function %f28(i64) -> i64 {
@@ -629,14 +623,14 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   li t2,-1
+;   li a1,-1
-;   sub a0,a0,t2
+;   sub a0,a0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t2, zero, -1
+;   addi a1, zero, -1
-;   sub a0, a0, t2
+;   sub a0, a0, a1
 ;   ret
 
 function %f29(i64) -> i64 {
@@ -648,14 +642,14 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   li t2,1
+;   li a0,1
-;   sub a0,zero,t2
+;   sub a0,zero,a0
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t2, zero, 1
+;   addi a0, zero, 1
-;   neg a0, t2
+;   neg a0, a0
 ;   ret
 
 function %add_i128(i128, i128) -> i128 {
@@ -810,19 +804,17 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   li t2,2
+;   li a1,2
-;   trap_ifc int_divz##(zero eq t2)
+;   trap_ifc int_divz##(zero eq a1)
-;   li a2,2
+;   rem a0,a0,a1
-;   rem a0,a0,a2
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t2, zero, 2
+;   addi a1, zero, 2
-;   bne zero, t2, 8
+;   bne zero, a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
-;   addi a2, zero, 2
+;   rem a0, a0, a1
-;   rem a0, a0, a2
 ;   ret
 
 function %urem_const (i64) -> i64 {
@@ -834,19 +826,17 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   li t2,2
+;   li a1,2
-;   trap_ifc int_divz##(zero eq t2)
+;   trap_ifc int_divz##(zero eq a1)
-;   li a2,2
+;   remu a0,a0,a1
-;   remu a0,a0,a2
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t2, zero, 2
+;   addi a1, zero, 2
-;   bne zero, t2, 8
+;   bne zero, a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
-;   addi a2, zero, 2
+;   remu a0, a0, a1
-;   remu a0, a0, a2
 ;   ret
 
 function %sdiv_minus_one(i64) -> i64 {
@@ -858,41 +848,37 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   li t2,-1
+;   li a6,-1
 ;   li a1,-1
-;   li a3,1
+;   li a2,1
-;   slli a5,a3,63
+;   slli a4,a2,63
-;   eq a7,a1,t2##ty=i64
+;   eq a7,a1,a6##ty=i64
-;   eq t4,a5,a0##ty=i64
+;   eq t3,a4,a0##ty=i64
-;   and t1,a7,t4
+;   and t0,a7,t3
-;   trap_if t1,int_ovf
+;   trap_if t0,int_ovf
-;   li a1,-1
+;   trap_ifc int_divz##(zero eq a6)
-;   trap_ifc int_divz##(zero eq a1)
+;   div a0,a0,a6
-;   li a4,-1
-;   div a0,a0,a4
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t2, zero, -1
+;   addi a6, zero, -1
 ;   addi a1, zero, -1
-;   addi a3, zero, 1
+;   addi a2, zero, 1
-;   slli a5, a3, 0x3f
+;   slli a4, a2, 0x3f
-;   bne a1, t2, 0xc
+;   bne a1, a6, 0xc
 ;   addi a7, zero, 1
 ;   j 8
 ;   mv a7, zero
-;   bne a5, a0, 0xc
+;   bne a4, a0, 0xc
-;   addi t4, zero, 1
+;   addi t3, zero, 1
 ;   j 8
-;   mv t4, zero
+;   mv t3, zero
-;   and t1, a7, t4
+;   and t0, a7, t3
-;   beqz t1, 8
+;   beqz t0, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_ovf
-;   addi a1, zero, -1
+;   bne zero, a6, 8
-;   bne zero, a1, 8
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; trap: int_divz
-;   addi a4, zero, -1
+;   div a0, a0, a6
-;   div a0, a0, a4
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/bitops-float.clif

@@ -21,59 +21,53 @@ block1(v4: f32):
 
 ; VCode:
 ; block0:
-;   li a1,0
+;   li a0,0
-;   fmv.w.x ft9,a1
 ;   li t1,0
 ;   fmv.w.x fa6,t1
-;   fmv.x.w a1,fa6
+;   fmv.x.w t4,fa6
-;   not a3,a1
+;   not t1,t4
-;   fmv.w.x ft1,a3
+;   fmv.w.x ft8,t1
-;   fmv.x.w t1,ft1
+;   fmv.x.w t3,ft8
-;   fmv.x.w a0,ft1
+;   fmv.x.w t0,ft8
-;   or a2,t1,a0
+;   or t2,t3,t0
-;   fmv.w.x fa2,a2
+;   fmv.w.x fa1,t2
-;   li t2,0
+;   br_table a0,[MachLabel(1),MachLabel(2)]##tmp1=t0,tmp2=t1
-;   br_table t2,[MachLabel(1),MachLabel(2)]##tmp1=a1,tmp2=a2
 ; block1:
 ;   j label3
 ; block2:
-;   fmv.d fa2,ft9
+;   fmv.d fa1,fa6
 ;   j label3
 ; block3:
-;   li a0,0
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mv a1, zero
+;   mv a0, zero
-;   fmv.w.x ft9, a1
 ;   mv t1, zero
 ;   fmv.w.x fa6, t1
-;   fmv.x.w a1, fa6
+;   fmv.x.w t4, fa6
-;   not a3, a1
+;   not t1, t4
-;   fmv.w.x ft1, a3
+;   fmv.w.x ft8, t1
-;   fmv.x.w t1, ft1
+;   fmv.x.w t3, ft8
-;   fmv.x.w a0, ft1
+;   fmv.x.w t0, ft8
-;   or a2, t1, a0
+;   or t2, t3, t0
-;   fmv.w.x fa2, a2
+;   fmv.w.x fa1, t2
-;   mv t2, zero
+;   slli t6, a0, 0x20
-;   slli t6, t2, 0x20
 ;   srli t6, t6, 0x20
-;   addi a2, zero, 1
+;   addi t1, zero, 1
-;   bltu t6, a2, 0xc
+;   bltu t6, t1, 0xc
-;   auipc a2, 0
+;   auipc t1, 0
-;   jalr zero, a2, 0x28
+;   jalr zero, t1, 0x28
-;   auipc a1, 0
+;   auipc t0, 0
-;   slli a2, t6, 3
+;   slli t1, t6, 3
-;   add a1, a1, a2
+;   add t0, t0, t1
-;   jalr zero, a1, 0x10
+;   jalr zero, t0, 0x10
-;   auipc a2, 0
+;   auipc t1, 0
-;   jalr zero, a2, 0xc
+;   jalr zero, t1, 0xc
-; block1: ; offset 0x60
+; block1: ; offset 0x58
 ;   j 8
-; block2: ; offset 0x64
+; block2: ; offset 0x5c
-;   fmv.d fa2, ft9
+;   fmv.d fa1, fa6
-; block3: ; offset 0x68
+; block3: ; offset 0x60
-;   mv a0, zero
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/bitops.clif

@@ -1458,15 +1458,15 @@ block0(v0: i64):
 ; VCode:
 ; block0:
 ;   li a1,4
-;   not a2,a1
+;   not a1,a1
-;   and a0,a0,a2
+;   and a0,a0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi a1, zero, 4
-;   not a2, a1
+;   not a1, a1
-;   and a0, a0, a2
+;   and a0, a0, a1
 ;   ret
 
 function %band_not_i64_constant_shift(i64, i64) -> i64 {
@@ -1559,15 +1559,15 @@ block0(v0: i64):
 ; VCode:
 ; block0:
 ;   li a1,4
-;   not a2,a1
+;   not a1,a1
-;   or a0,a0,a2
+;   or a0,a0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi a1, zero, 4
-;   not a2, a1
+;   not a1, a1
-;   or a0, a0, a2
+;   or a0, a0, a1
 ;   ret
 
 function %bor_not_i64_constant_shift(i64, i64) -> i64 {
@@ -1660,15 +1660,15 @@ block0(v0: i64):
 ; VCode:
 ; block0:
 ;   li a1,4
-;   not a2,a1
+;   not a1,a1
-;   xor a0,a0,a2
+;   xor a0,a0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
 ;   addi a1, zero, 4
-;   not a2, a1
+;   not a1, a1
-;   xor a0, a0, a2
+;   xor a0, a0, a1
 ;   ret
 
 function %bxor_not_i64_constant_shift(i64, i64) -> i64 {

cranelift/filetests/filetests/isa/riscv64/call.clif

@@ -172,20 +172,19 @@ block0(v0: i8):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   mv t3,a0
+;   li a7,42
 ;   add sp,-16
 ;   virtual_sp_offset_adj +16
-;   li a0,42
+;   slli a2,a0,56; srai a2,a2,56
-;   li a1,42
+;   sd a2,0(sp)
-;   li a2,42
-;   li a3,42
-;   li a4,42
-;   li a5,42
-;   li a6,42
-;   li a7,42
-;   slli t3,t3,56; srai t3,t3,56
-;   sd t3,0(sp)
 ;   load_sym t3,%g+0
+;   mv a0,a7
+;   mv a1,a7
+;   mv a2,a7
+;   mv a3,a7
+;   mv a4,a7
+;   mv a5,a7
+;   mv a6,a7
 ;   callind t3
 ;   add sp,+16
 ;   virtual_sp_offset_adj -16
@@ -201,24 +200,23 @@ block0(v0: i8):
 ;   sd s0, 0(sp)
 ;   ori s0, sp, 0
 ; block1: ; offset 0x10
-;   ori t3, a0, 0
-;   addi sp, sp, -0x10
-;   addi a0, zero, 0x2a
-;   addi a1, zero, 0x2a
-;   addi a2, zero, 0x2a
-;   addi a3, zero, 0x2a
-;   addi a4, zero, 0x2a
-;   addi a5, zero, 0x2a
-;   addi a6, zero, 0x2a
 ;   addi a7, zero, 0x2a
-;   slli t3, t3, 0x38
+;   addi sp, sp, -0x10
-;   srai t3, t3, 0x38
+;   slli a2, a0, 0x38
-;   sd t3, 0(sp)
+;   srai a2, a2, 0x38
+;   sd a2, 0(sp)
 ;   auipc t3, 0
 ;   ld t3, 0xc(t3)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %g 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
+;   ori a0, a7, 0
+;   ori a1, a7, 0
+;   ori a2, a7, 0
+;   ori a3, a7, 0
+;   ori a4, a7, 0
+;   ori a5, a7, 0
+;   ori a6, a7, 0
 ;   jalr t3
 ;   addi sp, sp, 0x10
 ;   ld ra, 8(sp)
@@ -234,51 +232,35 @@ block0(v0: i8):
 
 ; VCode:
 ; block0:
-;   li a2,42
+;   mv a2,a1
-;   mv t1,a2
+;   li a1,42
-;   li a2,42
 ;   mv a3,a2
-;   li a4,42
+;   sw a1,0(a3)
-;   li a6,42
+;   sw a1,8(a3)
-;   li t3,42
+;   sw a1,16(a3)
-;   li t0,42
+;   sw a1,24(a3)
-;   li t2,42
+;   sw a1,32(a3)
-;   li a2,42
+;   sw a1,40(a3)
-;   sw a4,0(a1)
+;   slli a7,a0,56; srai a7,a7,56
-;   sw a6,8(a1)
+;   sd a0,48(a3)
-;   sw t3,16(a1)
+;   mv a0,a1
-;   sw t0,24(a1)
-;   sw t2,32(a1)
-;   sw a2,40(a1)
-;   slli t4,a0,56; srai t4,t4,56
-;   sd a0,48(a1)
-;   mv a0,t1
-;   mv a1,a3
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi a2, zero, 0x2a
+;   ori a2, a1, 0
-;   ori t1, a2, 0
+;   addi a1, zero, 0x2a
-;   addi a2, zero, 0x2a
 ;   ori a3, a2, 0
-;   addi a4, zero, 0x2a
+;   sw a1, 0(a3)
-;   addi a6, zero, 0x2a
+;   sw a1, 8(a3)
-;   addi t3, zero, 0x2a
+;   sw a1, 0x10(a3)
-;   addi t0, zero, 0x2a
+;   sw a1, 0x18(a3)
-;   addi t2, zero, 0x2a
+;   sw a1, 0x20(a3)
-;   addi a2, zero, 0x2a
+;   sw a1, 0x28(a3)
-;   sw a4, 0(a1)
+;   slli a7, a0, 0x38
-;   sw a6, 8(a1)
+;   srai a7, a7, 0x38
-;   sw t3, 0x10(a1)
+;   sd a0, 0x30(a3)
-;   sw t0, 0x18(a1)
+;   ori a0, a1, 0
-;   sw t2, 0x20(a1)
-;   sw a2, 0x28(a1)
-;   slli t4, a0, 0x38
-;   srai t4, t4, 0x38
-;   sd a0, 0x30(a1)
-;   ori a0, t1, 0
-;   ori a1, a3, 0
 ;   ret
 
 function %f8() {
@@ -438,12 +420,12 @@ block0(v0: i64):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   mv a5,a0
+;   mv a4,a0
-;   li a0,42
-;   mv a1,a5
 ;   li a2,42
-;   load_sym a5,%f11+0
+;   mv a0,a2
-;   callind a5
+;   mv a1,a4
+;   load_sym a3,%f11+0
+;   callind a3
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -456,16 +438,16 @@ block0(v0: i64):
 ;   sd s0, 0(sp)
 ;   ori s0, sp, 0
 ; block1: ; offset 0x10
-;   ori a5, a0, 0
+;   ori a4, a0, 0
-;   addi a0, zero, 0x2a
-;   ori a1, a5, 0
 ;   addi a2, zero, 0x2a
-;   auipc a5, 0
+;   ori a0, a2, 0
-;   ld a5, 0xc(a5)
+;   ori a1, a4, 0
+;   auipc a3, 0
+;   ld a3, 0xc(a3)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f11 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   jalr a5
+;   jalr a3
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
@@ -505,11 +487,12 @@ block0(v0: i64):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   mv a1,a0
+;   mv a4,a0
-;   li a2,42
 ;   li a0,42
-;   load_sym a5,%f12+0
+;   mv a1,a4
-;   callind a5
+;   mv a2,a0
+;   load_sym a3,%f12+0
+;   callind a3
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -522,15 +505,16 @@ block0(v0: i64):
 ;   sd s0, 0(sp)
 ;   ori s0, sp, 0
 ; block1: ; offset 0x10
-;   ori a1, a0, 0
+;   ori a4, a0, 0
-;   addi a2, zero, 0x2a
 ;   addi a0, zero, 0x2a
-;   auipc a5, 0
+;   ori a1, a4, 0
-;   ld a5, 0xc(a5)
+;   ori a2, a0, 0
+;   auipc a3, 0
+;   ld a3, 0xc(a3)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f12 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   jalr a5
+;   jalr a3
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10
@@ -570,11 +554,12 @@ block0(v0: i64):
 ;   sd fp,0(sp)
 ;   mv fp,sp
 ; block0:
-;   mv a1,a0
+;   mv a4,a0
-;   li a2,42
 ;   li a0,42
-;   load_sym a5,%f13+0
+;   mv a1,a4
-;   callind a5
+;   mv a2,a0
+;   load_sym a3,%f13+0
+;   callind a3
 ;   ld ra,8(sp)
 ;   ld fp,0(sp)
 ;   add sp,+16
@@ -587,15 +572,16 @@ block0(v0: i64):
 ;   sd s0, 0(sp)
 ;   ori s0, sp, 0
 ; block1: ; offset 0x10
-;   ori a1, a0, 0
+;   ori a4, a0, 0
-;   addi a2, zero, 0x2a
 ;   addi a0, zero, 0x2a
-;   auipc a5, 0
+;   ori a1, a4, 0
-;   ld a5, 0xc(a5)
+;   ori a2, a0, 0
+;   auipc a3, 0
+;   ld a3, 0xc(a3)
 ;   j 0xc
 ;   .byte 0x00, 0x00, 0x00, 0x00 ; reloc_external Abs8 %f13 0
 ;   .byte 0x00, 0x00, 0x00, 0x00
-;   jalr a5
+;   jalr a3
 ;   ld ra, 8(sp)
 ;   ld s0, 0(sp)
 ;   addi sp, sp, 0x10

cranelift/filetests/filetests/isa/riscv64/condops.clif

@@ -12,18 +12,18 @@ block0(v0: i8, v1: i64, v2: i64):
 
 ; VCode:
 ; block0:
-;   andi a3,a0,255
 ;   li a4,42
-;   andi a5,a4,255
+;   andi a3,a0,255
-;   select_reg a0,a1,a2##condition=(a3 eq a5)
+;   andi a4,a4,255
+;   select_reg a0,a1,a2##condition=(a3 eq a4)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   andi a3, a0, 0xff
 ;   addi a4, zero, 0x2a
-;   andi a5, a4, 0xff
+;   andi a3, a0, 0xff
-;   beq a3, a5, 0xc
+;   andi a4, a4, 0xff
+;   beq a3, a4, 0xc
 ;   ori a0, a2, 0
 ;   j 8
 ;   ori a0, a1, 0
@@ -38,18 +38,18 @@ block0(v0: i8):
 
 ; VCode:
 ; block0:
-;   li t2,42
+;   li a2,42
-;   andi a1,a0,255
+;   andi a0,a0,255
-;   andi a3,t2,255
+;   andi a2,a2,255
-;   eq a0,a1,a3##ty=i8
+;   eq a0,a0,a2##ty=i8
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t2, zero, 0x2a
+;   addi a2, zero, 0x2a
-;   andi a1, a0, 0xff
+;   andi a0, a0, 0xff
-;   andi a3, t2, 0xff
+;   andi a2, a2, 0xff
-;   bne a1, a3, 0xc
+;   bne a0, a2, 0xc
 ;   addi a0, zero, 1
 ;   j 8
 ;   mv a0, zero
@@ -108,22 +108,22 @@ block0(v0: i32, v1: i8, v2: i8):
 
 ; VCode:
 ; block0:
+;   li a6,42
 ;   slli a3,a0,32
-;   srli a3,a3,32
+;   srli a4,a3,32
-;   li a5,42
+;   slli a6,a6,32
-;   slli a7,a5,32
+;   srli t3,a6,32
-;   srli t4,a7,32
+;   select_reg a0,a1,a2##condition=(a4 eq t3)
-;   select_reg a0,a1,a2##condition=(a3 eq t4)
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
+;   addi a6, zero, 0x2a
 ;   slli a3, a0, 0x20
-;   srli a3, a3, 0x20
+;   srli a4, a3, 0x20
-;   addi a5, zero, 0x2a
+;   slli a6, a6, 0x20
-;   slli a7, a5, 0x20
+;   srli t3, a6, 0x20
-;   srli t4, a7, 0x20
+;   beq a4, t3, 0xc
-;   beq a3, t4, 0xc
 ;   ori a0, a2, 0
 ;   j 8
 ;   ori a0, a1, 0

cranelift/filetests/filetests/isa/riscv64/fcmp.clif

@@ -14,12 +14,10 @@ block1:
 
 ; VCode:
 ; block0:
-;   li t1,0
+;   li t2,0
-;   fmv.d.x ft1,t1
+;   fmv.d.x ft2,t2
-;   li a2,0
+;   fle.d t2,ft2,ft2
-;   fmv.d.x ft5,a2
+;   bne t2,zero,taken(label2),not_taken(label1)
-;   fle.d a5,ft5,ft1
-;   bne a5,zero,taken(label2),not_taken(label1)
 ; block1:
 ;   j label3
 ; block2:
@@ -29,12 +27,10 @@ block1:
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mv t1, zero
+;   mv t2, zero
-;   fmv.d.x ft1, t1
+;   fmv.d.x ft2, t2
-;   mv a2, zero
+;   fle.d t2, ft2, ft2
-;   fmv.d.x ft5, a2
+; block1: ; offset 0xc
-;   fle.d a5, ft5, ft1
-; block1: ; offset 0x14
 ;   ret
 
 function %f1() {
@@ -49,12 +45,10 @@ block1:
 
 ; VCode:
 ; block0:
-;   li t1,0
+;   li t2,0
-;   fmv.d.x ft1,t1
+;   fmv.d.x ft2,t2
-;   li a2,0
+;   fle.d t2,ft2,ft2
-;   fmv.d.x ft5,a2
+;   bne t2,zero,taken(label2),not_taken(label1)
-;   fle.d a5,ft5,ft1
-;   bne a5,zero,taken(label2),not_taken(label1)
 ; block1:
 ;   j label3
 ; block2:
@@ -64,11 +58,9 @@ block1:
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   mv t1, zero
+;   mv t2, zero
-;   fmv.d.x ft1, t1
+;   fmv.d.x ft2, t2
-;   mv a2, zero
+;   fle.d t2, ft2, ft2
-;   fmv.d.x ft5, a2
+; block1: ; offset 0xc
-;   fle.d a5, ft5, ft1
-; block1: ; offset 0x14
 ;   ret
 

cranelift/filetests/filetests/isa/riscv64/iconst-icmp-small.clif

@@ -12,28 +12,24 @@ block0:
 
 ; VCode:
 ; block0:
-;   lui t1,14
+;   lui a3,14
-;   addi t1,t1,3532
+;   addi a3,a3,3532
-;   lui a2,14
+;   slli t2,a3,48
-;   addi a2,a2,3532
+;   srli a1,t2,48
-;   slli a5,t1,48
+;   slli a3,a3,48
-;   srli a7,a5,48
+;   srli a5,a3,48
-;   slli t4,a2,48
+;   ne a0,a1,a5##ty=i16
-;   srli t1,t4,48
-;   ne a0,a7,t1##ty=i16
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   lui t1, 0xe
+;   lui a3, 0xe
-;   addi t1, t1, -0x234
+;   addi a3, a3, -0x234
-;   lui a2, 0xe
+;   slli t2, a3, 0x30
-;   addi a2, a2, -0x234
+;   srli a1, t2, 0x30
-;   slli a5, t1, 0x30
+;   slli a3, a3, 0x30
-;   srli a7, a5, 0x30
+;   srli a5, a3, 0x30
-;   slli t4, a2, 0x30
+;   beq a1, a5, 0xc
-;   srli t1, t4, 0x30
-;   beq a7, t1, 0xc
 ;   addi a0, zero, 1
 ;   j 8
 ;   mv a0, zero

cranelift/filetests/filetests/isa/riscv64/shift-rotate.clif

@@ -621,29 +621,29 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   li t2,17
+;   li a6,17
-;   andi a1,t2,63
+;   andi a1,a6,63
-;   li a3,64
+;   li a2,64
-;   sub a5,a3,a1
+;   sub a4,a2,a1
-;   srl a7,a0,a1
+;   srl a6,a0,a1
-;   sll t4,a0,a5
+;   sll t3,a0,a4
-;   select_reg t1,zero,t4##condition=(a1 eq zero)
+;   select_reg t0,zero,t3##condition=(a1 eq zero)
-;   or a0,a7,t1
+;   or a0,a6,t0
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t2, zero, 0x11
+;   addi a6, zero, 0x11
-;   andi a1, t2, 0x3f
+;   andi a1, a6, 0x3f
-;   addi a3, zero, 0x40
+;   addi a2, zero, 0x40
-;   sub a5, a3, a1
+;   sub a4, a2, a1
-;   srl a7, a0, a1
+;   srl a6, a0, a1
-;   sll t4, a0, a5
+;   sll t3, a0, a4
 ;   beqz a1, 0xc
-;   ori t1, t4, 0
+;   ori t0, t3, 0
 ;   j 8
-;   ori t1, zero, 0
+;   ori t0, zero, 0
-;   or a0, a7, t1
+;   or a0, a6, t0
 ;   ret
 
 function %f21(i64) -> i64 {
@@ -655,29 +655,29 @@ block0(v0: i64):
 
 ; VCode:
 ; block0:
-;   li t2,17
+;   li a6,17
-;   andi a1,t2,63
+;   andi a1,a6,63
-;   li a3,64
+;   li a2,64
-;   sub a5,a3,a1
+;   sub a4,a2,a1
-;   sll a7,a0,a1
+;   sll a6,a0,a1
-;   srl t4,a0,a5
+;   srl t3,a0,a4
-;   select_reg t1,zero,t4##condition=(a1 eq zero)
+;   select_reg t0,zero,t3##condition=(a1 eq zero)
-;   or a0,a7,t1
+;   or a0,a6,t0
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   addi t2, zero, 0x11
+;   addi a6, zero, 0x11
-;   andi a1, t2, 0x3f
+;   andi a1, a6, 0x3f
-;   addi a3, zero, 0x40
+;   addi a2, zero, 0x40
-;   sub a5, a3, a1
+;   sub a4, a2, a1
-;   sll a7, a0, a1
+;   sll a6, a0, a1
-;   srl t4, a0, a5
+;   srl t3, a0, a4
 ;   beqz a1, 0xc
-;   ori t1, t4, 0
+;   ori t0, t3, 0
 ;   j 8
-;   ori t1, zero, 0
+;   ori t0, zero, 0
-;   or a0, a7, t1
+;   or a0, a6, t0
 ;   ret
 
 function %f22(i32) -> i32 {
@@ -689,33 +689,33 @@ block0(v0: i32):
 
 ; VCode:
 ; block0:
-;   slli t2,a0,32
+;   li t3,17
-;   srli a1,t2,32
+;   slli a0,a0,32
-;   li a3,17
+;   srli a2,a0,32
-;   andi a5,a3,31
+;   andi a4,t3,31
-;   li a7,32
+;   li a6,32
-;   sub t4,a7,a5
+;   sub t3,a6,a4
-;   sll t1,a1,a5
+;   sll t0,a2,a4
-;   srl a0,a1,t4
+;   srl t2,a2,t3
-;   select_reg a2,zero,a0##condition=(a5 eq zero)
+;   select_reg a1,zero,t2##condition=(a4 eq zero)
-;   or a0,t1,a2
+;   or a0,t0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli t2, a0, 0x20
+;   addi t3, zero, 0x11
-;   srli a1, t2, 0x20
+;   slli a0, a0, 0x20
-;   addi a3, zero, 0x11
+;   srli a2, a0, 0x20
-;   andi a5, a3, 0x1f
+;   andi a4, t3, 0x1f
-;   addi a7, zero, 0x20
+;   addi a6, zero, 0x20
-;   sub t4, a7, a5
+;   sub t3, a6, a4
-;   sll t1, a1, a5
+;   sll t0, a2, a4
-;   srl a0, a1, t4
+;   srl t2, a2, t3
-;   beqz a5, 0xc
+;   beqz a4, 0xc
-;   ori a2, a0, 0
+;   ori a1, t2, 0
 ;   j 8
-;   ori a2, zero, 0
+;   ori a1, zero, 0
-;   or a0, t1, a2
+;   or a0, t0, a1
 ;   ret
 
 function %f23(i16) -> i16 {
@@ -727,33 +727,33 @@ block0(v0: i16):
 
 ; VCode:
 ; block0:
-;   slli t2,a0,48
+;   li t3,10
-;   srli a1,t2,48
+;   slli a0,a0,48
-;   li a3,10
+;   srli a2,a0,48
-;   andi a5,a3,15
+;   andi a4,t3,15
-;   li a7,16
+;   li a6,16
-;   sub t4,a7,a5
+;   sub t3,a6,a4
-;   sll t1,a1,a5
+;   sll t0,a2,a4
-;   srl a0,a1,t4
+;   srl t2,a2,t3
-;   select_reg a2,zero,a0##condition=(a5 eq zero)
+;   select_reg a1,zero,t2##condition=(a4 eq zero)
-;   or a0,t1,a2
+;   or a0,t0,a1
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   slli t2, a0, 0x30
+;   addi t3, zero, 0xa
-;   srli a1, t2, 0x30
+;   slli a0, a0, 0x30
-;   addi a3, zero, 0xa
+;   srli a2, a0, 0x30
-;   andi a5, a3, 0xf
+;   andi a4, t3, 0xf
-;   addi a7, zero, 0x10
+;   addi a6, zero, 0x10
-;   sub t4, a7, a5
+;   sub t3, a6, a4
-;   sll t1, a1, a5
+;   sll t0, a2, a4
-;   srl a0, a1, t4
+;   srl t2, a2, t3
-;   beqz a5, 0xc
+;   beqz a4, 0xc
-;   ori a2, a0, 0
+;   ori a1, t2, 0
 ;   j 8
-;   ori a2, zero, 0
+;   ori a1, zero, 0
-;   or a0, t1, a2
+;   or a0, t0, a1
 ;   ret
 
 function %f24(i8) -> i8 {
@@ -765,31 +765,31 @@ block0(v0: i8):
 
 ; VCode:
 ; block0:
-;   andi t2,a0,255
+;   li a7,3
-;   li a1,3
+;   andi a0,a0,255
-;   andi a3,a1,7
+;   andi a2,a7,7
-;   li a5,8
+;   li a4,8
-;   sub a7,a5,a3
+;   sub a6,a4,a2
-;   sll t4,t2,a3
+;   sll t3,a0,a2
-;   srl t1,t2,a7
+;   srl t0,a0,a6
-;   select_reg a0,zero,t1##condition=(a3 eq zero)
+;   select_reg t2,zero,t0##condition=(a2 eq zero)
-;   or a0,t4,a0
+;   or a0,t3,t2
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   andi t2, a0, 0xff
+;   addi a7, zero, 3
-;   addi a1, zero, 3
+;   andi a0, a0, 0xff
-;   andi a3, a1, 7
+;   andi a2, a7, 7
-;   addi a5, zero, 8
+;   addi a4, zero, 8
-;   sub a7, a5, a3
+;   sub a6, a4, a2
-;   sll t4, t2, a3
+;   sll t3, a0, a2
-;   srl t1, t2, a7
+;   srl t0, a0, a6
-;   beqz a3, 0xc
+;   beqz a2, 0xc
-;   ori a0, t1, 0
+;   ori t2, t0, 0
 ;   j 8
-;   ori a0, zero, 0
+;   ori t2, zero, 0
-;   or a0, t4, a0
+;   or a0, t3, t2
 ;   ret
 
 function %f25(i64) -> i64 {

cranelift/filetests/filetests/isa/riscv64/stack.clif

@@ -448,157 +448,179 @@ block0(v0: i8):
 ;   sd s9,-72(sp)
 ;   sd s10,-80(sp)
 ;   sd s11,-88(sp)
-;   add sp,-1280
+;   add sp,-1360
 ; block0:
 ;   sd a0,1000(nominal_sp)
-;   li t3,2
+;   li t0,2
-;   addi t1,t3,1
+;   sd t0,1008(nominal_sp)
-;   sd t1,1176(nominal_sp)
+;   li t0,4
-;   li t3,4
+;   li t1,6
-;   addi t2,t3,3
+;   li t2,8
-;   sd t2,1168(nominal_sp)
+;   li a1,10
-;   li t3,6
+;   li a2,12
-;   addi a1,t3,5
+;   li a3,14
-;   sd a1,1160(nominal_sp)
+;   li a4,16
-;   li t3,8
+;   li a5,18
-;   addi a2,t3,7
+;   li a6,20
-;   sd a2,1152(nominal_sp)
+;   li a7,22
-;   li t3,10
-;   addi a3,t3,9
-;   sd a3,1144(nominal_sp)
-;   li t3,12
-;   addi a4,t3,11
-;   sd a4,1136(nominal_sp)
-;   li t3,14
-;   addi a5,t3,13
-;   sd a5,1128(nominal_sp)
-;   li t3,16
-;   addi a6,t3,15
-;   sd a6,1120(nominal_sp)
-;   li t3,18
-;   addi a7,t3,17
-;   sd a7,1112(nominal_sp)
-;   li t3,20
-;   addi t3,t3,19
-;   sd t3,1104(nominal_sp)
-;   li t3,22
-;   addi t4,t3,21
-;   sd t4,1096(nominal_sp)
 ;   li t3,24
-;   addi s6,t3,23
+;   li s5,26
-;   sd s6,1088(nominal_sp)
+;   li s6,28
-;   li t3,26
+;   li s7,30
-;   addi s7,t3,25
+;   li s8,32
-;   sd s7,1080(nominal_sp)
+;   li s9,34
-;   li t3,28
+;   li s10,36
-;   addi s8,t3,27
+;   li s11,38
-;   sd s8,1072(nominal_sp)
+;   li s1,30
-;   li t3,30
+;   li s2,32
-;   addi s9,t3,29
+;   li s3,34
-;   sd s9,1064(nominal_sp)
+;   li s4,36
-;   li t3,32
+;   li a0,38
-;   addi s10,t3,31
+;   li t4,30
-;   sd s10,1056(nominal_sp)
+;   sd t4,1256(nominal_sp)
-;   li t3,34
+;   li t4,32
-;   addi s11,t3,33
+;   sd t4,1248(nominal_sp)
-;   sd s11,1048(nominal_sp)
+;   li t4,34
-;   li t3,36
+;   sd t4,1240(nominal_sp)
-;   addi s1,t3,35
+;   li t4,36
-;   sd s1,1040(nominal_sp)
+;   sd t4,1232(nominal_sp)
-;   li t3,38
+;   li t4,38
-;   addi s2,t3,37
+;   sd t4,1224(nominal_sp)
-;   sd s2,1032(nominal_sp)
+;   li t4,30
-;   li t3,30
+;   sd t4,1216(nominal_sp)
-;   addi s3,t3,39
+;   li t4,32
-;   sd s3,1024(nominal_sp)
+;   sd t4,1208(nominal_sp)
-;   li t3,32
+;   li t4,34
-;   addi s4,t3,31
+;   sd t4,1200(nominal_sp)
-;   sd s4,1016(nominal_sp)
+;   li t4,36
-;   li t3,34
+;   sd t4,1192(nominal_sp)
-;   addi s5,t3,33
+;   li t4,38
-;   sd s5,1008(nominal_sp)
+;   sd t4,1184(nominal_sp)
-;   li t3,36
+;   ld t4,1008(nominal_sp)
-;   addi s5,t3,35
+;   addi t4,t4,1
-;   li t3,38
+;   sd t4,1176(nominal_sp)
-;   addi a0,t3,37
+;   addi t4,t0,3
-;   li t3,30
+;   sd t4,1168(nominal_sp)
-;   addi t0,t3,39
+;   addi t4,t1,5
-;   li t3,32
+;   sd t4,1160(nominal_sp)
-;   addi t1,t3,31
+;   addi t4,t2,7
-;   li t3,34
+;   sd t4,1152(nominal_sp)
-;   addi t2,t3,33
+;   addi t4,a1,9
-;   li t3,36
+;   sd t4,1144(nominal_sp)
-;   addi a1,t3,35
+;   addi t4,a2,11
-;   li t3,38
+;   sd t4,1136(nominal_sp)
-;   addi a2,t3,37
+;   addi t4,a3,13
-;   li t3,30
+;   sd t4,1128(nominal_sp)
-;   addi a3,t3,39
+;   addi t4,a4,15
-;   li t3,32
+;   sd t4,1120(nominal_sp)
-;   addi a4,t3,31
+;   addi t4,a5,17
-;   li t3,34
+;   sd t4,1112(nominal_sp)
-;   addi a5,t3,33
+;   addi t4,a6,19
-;   li t3,36
+;   sd t4,1104(nominal_sp)
-;   addi a6,t3,35
+;   addi t4,a7,21
-;   li t3,38
+;   sd t4,1096(nominal_sp)
-;   addi a7,t3,37
+;   addi t4,t3,23
-;   ld t3,1176(nominal_sp)
+;   sd t4,1088(nominal_sp)
-;   addi t3,t3,39
+;   addi t4,s5,25
-;   ld t4,1160(nominal_sp)
+;   sd t4,1080(nominal_sp)
-;   ld s2,1168(nominal_sp)
+;   addi t4,s6,27
-;   add t4,s2,t4
+;   sd t4,1072(nominal_sp)
-;   ld s9,1144(nominal_sp)
+;   addi t4,s7,29
-;   ld s7,1152(nominal_sp)
+;   sd t4,1064(nominal_sp)
-;   add s6,s7,s9
+;   addi t4,s8,31
-;   ld s3,1128(nominal_sp)
+;   sd t4,1056(nominal_sp)
-;   ld s1,1136(nominal_sp)
+;   addi t4,s9,33
-;   add s7,s1,s3
+;   sd t4,1048(nominal_sp)
-;   ld s8,1112(nominal_sp)
+;   addi t4,s10,35
-;   ld s9,1120(nominal_sp)
+;   sd t4,1040(nominal_sp)
-;   add s8,s9,s8
+;   addi t4,s11,37
-;   ld s2,1096(nominal_sp)
+;   sd t4,1032(nominal_sp)
-;   ld s11,1104(nominal_sp)
+;   addi t4,s1,39
-;   add s9,s11,s2
+;   sd t4,1024(nominal_sp)
-;   ld s10,1080(nominal_sp)
+;   addi t4,s2,31
-;   ld s11,1088(nominal_sp)
+;   sd t4,1016(nominal_sp)
-;   add s10,s11,s10
+;   addi t4,s3,33
-;   ld s1,1064(nominal_sp)
+;   sd t4,1008(nominal_sp)
+;   addi s4,s4,35
+;   addi a0,a0,37
+;   ld t4,1256(nominal_sp)
+;   addi t4,t4,39
+;   ld t3,1248(nominal_sp)
+;   addi t0,t3,31
+;   ld t1,1240(nominal_sp)
+;   addi t1,t1,33
+;   ld a1,1232(nominal_sp)
+;   addi t2,a1,35
+;   ld a4,1224(nominal_sp)
+;   addi a1,a4,37
+;   ld a7,1216(nominal_sp)
+;   addi a2,a7,39
+;   ld a3,1208(nominal_sp)
+;   addi a3,a3,31
+;   ld a4,1200(nominal_sp)
+;   addi a4,a4,33
+;   ld a5,1192(nominal_sp)
+;   addi a5,a5,35
+;   ld a6,1184(nominal_sp)
+;   addi a6,a6,37
+;   ld a7,1176(nominal_sp)
+;   addi a7,a7,39
+;   ld t3,1160(nominal_sp)
+;   ld s11,1168(nominal_sp)
+;   add t3,s11,t3
+;   ld s7,1144(nominal_sp)
+;   ld s5,1152(nominal_sp)
+;   add s5,s5,s7
+;   ld s1,1128(nominal_sp)
+;   ld s10,1136(nominal_sp)
+;   add s6,s10,s1
+;   ld s7,1112(nominal_sp)
+;   ld s8,1120(nominal_sp)
+;   add s7,s8,s7
+;   ld s11,1096(nominal_sp)
+;   ld s9,1104(nominal_sp)
+;   add s8,s9,s11
+;   ld s9,1080(nominal_sp)
+;   ld s3,1088(nominal_sp)
+;   add s9,s3,s9
+;   ld s10,1064(nominal_sp)
 ;   ld s11,1072(nominal_sp)
-;   add s11,s11,s1
+;   add s10,s11,s10
-;   ld s1,1048(nominal_sp)
+;   ld s11,1048(nominal_sp)
-;   ld s4,1056(nominal_sp)
+;   ld s2,1056(nominal_sp)
-;   add s1,s4,s1
+;   add s11,s2,s11
-;   ld s2,1032(nominal_sp)
+;   ld s1,1032(nominal_sp)
-;   ld s3,1040(nominal_sp)
+;   ld s2,1040(nominal_sp)
-;   add s2,s3,s2
+;   add s1,s2,s1
-;   ld s4,1016(nominal_sp)
+;   ld s3,1016(nominal_sp)
-;   ld s3,1024(nominal_sp)
+;   ld s2,1024(nominal_sp)
+;   add s2,s2,s3
+;   ld s3,1008(nominal_sp)
 ;   add s3,s3,s4
-;   ld s4,1008(nominal_sp)
+;   add t4,a0,t4
-;   add s5,s4,s5
+;   add t0,t0,t1
-;   add t0,a0,t0
+;   add t1,t2,a1
-;   add t1,t1,t2
+;   add t2,a2,a3
+;   add a0,a4,a5
+;   add a1,a6,a7
+;   add a2,t3,s5
+;   add a3,s6,s7
+;   add a4,s8,s9
+;   add a5,s10,s11
+;   add a6,s1,s2
+;   add t4,s3,t4
+;   add t0,t0,t1
+;   add t1,t2,a0
 ;   add t2,a1,a2
 ;   add a0,a3,a4
 ;   add a1,a5,a6
-;   add a2,a7,t3
+;   add t4,t4,t0
-;   add t4,t4,s6
+;   add t0,t1,t2
-;   add a3,s7,s8
-;   add a4,s9,s10
-;   add a5,s11,s1
-;   add a6,s2,s3
-;   add t0,s5,t0
-;   add t1,t1,t2
-;   add t2,a0,a1
-;   add t4,a2,t4
-;   add a0,a3,a4
-;   add a1,a5,a6
-;   add t0,t0,t1
-;   add t4,t2,t4
 ;   add t1,a0,a1
-;   add t4,t0,t4
+;   add t4,t4,t0
 ;   add a1,t1,t4
 ;   ld a0,1000(nominal_sp)
-;   add sp,+1280
+;   add sp,+1360
 ;   ld s1,-8(sp)
 ;   ld s2,-16(sp)
 ;   ld s3,-24(sp)
@@ -632,157 +654,179 @@ block0(v0: i8):
 ;   sd s9, -0x48(sp)
 ;   sd s10, -0x50(sp)
 ;   sd s11, -0x58(sp)
-;   addi sp, sp, -0x500
+;   addi sp, sp, -0x550
 ; block1: ; offset 0x40
 ;   sd a0, 0x3e8(sp)
-;   addi t3, zero, 2
+;   addi t0, zero, 2
-;   addi t1, t3, 1
+;   sd t0, 0x3f0(sp)
-;   sd t1, 0x498(sp)
+;   addi t0, zero, 4
-;   addi t3, zero, 4
+;   addi t1, zero, 6
-;   addi t2, t3, 3
+;   addi t2, zero, 8
-;   sd t2, 0x490(sp)
+;   addi a1, zero, 0xa
-;   addi t3, zero, 6
+;   addi a2, zero, 0xc
-;   addi a1, t3, 5
+;   addi a3, zero, 0xe
-;   sd a1, 0x488(sp)
+;   addi a4, zero, 0x10
-;   addi t3, zero, 8
+;   addi a5, zero, 0x12
-;   addi a2, t3, 7
+;   addi a6, zero, 0x14
-;   sd a2, 0x480(sp)
+;   addi a7, zero, 0x16
-;   addi t3, zero, 0xa
-;   addi a3, t3, 9
-;   sd a3, 0x478(sp)
-;   addi t3, zero, 0xc
-;   addi a4, t3, 0xb
-;   sd a4, 0x470(sp)
-;   addi t3, zero, 0xe
-;   addi a5, t3, 0xd
-;   sd a5, 0x468(sp)
-;   addi t3, zero, 0x10
-;   addi a6, t3, 0xf
-;   sd a6, 0x460(sp)
-;   addi t3, zero, 0x12
-;   addi a7, t3, 0x11
-;   sd a7, 0x458(sp)
-;   addi t3, zero, 0x14
-;   addi t3, t3, 0x13
-;   sd t3, 0x450(sp)
-;   addi t3, zero, 0x16
-;   addi t4, t3, 0x15
-;   sd t4, 0x448(sp)
 ;   addi t3, zero, 0x18
-;   addi s6, t3, 0x17
+;   addi s5, zero, 0x1a
-;   sd s6, 0x440(sp)
+;   addi s6, zero, 0x1c
-;   addi t3, zero, 0x1a
+;   addi s7, zero, 0x1e
-;   addi s7, t3, 0x19
+;   addi s8, zero, 0x20
-;   sd s7, 0x438(sp)
+;   addi s9, zero, 0x22
-;   addi t3, zero, 0x1c
+;   addi s10, zero, 0x24
-;   addi s8, t3, 0x1b
+;   addi s11, zero, 0x26
-;   sd s8, 0x430(sp)
+;   addi s1, zero, 0x1e
-;   addi t3, zero, 0x1e
+;   addi s2, zero, 0x20
-;   addi s9, t3, 0x1d
+;   addi s3, zero, 0x22
-;   sd s9, 0x428(sp)
+;   addi s4, zero, 0x24
-;   addi t3, zero, 0x20
+;   addi a0, zero, 0x26
-;   addi s10, t3, 0x1f
+;   addi t4, zero, 0x1e
-;   sd s10, 0x420(sp)
+;   sd t4, 0x4e8(sp)
-;   addi t3, zero, 0x22
+;   addi t4, zero, 0x20
-;   addi s11, t3, 0x21
+;   sd t4, 0x4e0(sp)
-;   sd s11, 0x418(sp)
+;   addi t4, zero, 0x22
-;   addi t3, zero, 0x24
+;   sd t4, 0x4d8(sp)
-;   addi s1, t3, 0x23
+;   addi t4, zero, 0x24
-;   sd s1, 0x410(sp)
+;   sd t4, 0x4d0(sp)
-;   addi t3, zero, 0x26
+;   addi t4, zero, 0x26
-;   addi s2, t3, 0x25
+;   sd t4, 0x4c8(sp)
-;   sd s2, 0x408(sp)
+;   addi t4, zero, 0x1e
-;   addi t3, zero, 0x1e
+;   sd t4, 0x4c0(sp)
-;   addi s3, t3, 0x27
+;   addi t4, zero, 0x20
-;   sd s3, 0x400(sp)
+;   sd t4, 0x4b8(sp)
-;   addi t3, zero, 0x20
+;   addi t4, zero, 0x22
-;   addi s4, t3, 0x1f
+;   sd t4, 0x4b0(sp)
-;   sd s4, 0x3f8(sp)
+;   addi t4, zero, 0x24
-;   addi t3, zero, 0x22
+;   sd t4, 0x4a8(sp)
-;   addi s5, t3, 0x21
+;   addi t4, zero, 0x26
-;   sd s5, 0x3f0(sp)
+;   sd t4, 0x4a0(sp)
-;   addi t3, zero, 0x24
+;   ld t4, 0x3f0(sp)
-;   addi s5, t3, 0x23
+;   addi t4, t4, 1
-;   addi t3, zero, 0x26
+;   sd t4, 0x498(sp)
-;   addi a0, t3, 0x25
+;   addi t4, t0, 3
-;   addi t3, zero, 0x1e
+;   sd t4, 0x490(sp)
-;   addi t0, t3, 0x27
+;   addi t4, t1, 5
-;   addi t3, zero, 0x20
+;   sd t4, 0x488(sp)
-;   addi t1, t3, 0x1f
+;   addi t4, t2, 7
-;   addi t3, zero, 0x22
+;   sd t4, 0x480(sp)
-;   addi t2, t3, 0x21
+;   addi t4, a1, 9
-;   addi t3, zero, 0x24
+;   sd t4, 0x478(sp)
-;   addi a1, t3, 0x23
+;   addi t4, a2, 0xb
-;   addi t3, zero, 0x26
+;   sd t4, 0x470(sp)
-;   addi a2, t3, 0x25
+;   addi t4, a3, 0xd
-;   addi t3, zero, 0x1e
+;   sd t4, 0x468(sp)
-;   addi a3, t3, 0x27
+;   addi t4, a4, 0xf
-;   addi t3, zero, 0x20
+;   sd t4, 0x460(sp)
-;   addi a4, t3, 0x1f
+;   addi t4, a5, 0x11
-;   addi t3, zero, 0x22
+;   sd t4, 0x458(sp)
-;   addi a5, t3, 0x21
+;   addi t4, a6, 0x13
-;   addi t3, zero, 0x24
+;   sd t4, 0x450(sp)
-;   addi a6, t3, 0x23
+;   addi t4, a7, 0x15
-;   addi t3, zero, 0x26
+;   sd t4, 0x448(sp)
-;   addi a7, t3, 0x25
+;   addi t4, t3, 0x17
-;   ld t3, 0x498(sp)
+;   sd t4, 0x440(sp)
-;   addi t3, t3, 0x27
+;   addi t4, s5, 0x19
-;   ld t4, 0x488(sp)
+;   sd t4, 0x438(sp)
-;   ld s2, 0x490(sp)
+;   addi t4, s6, 0x1b
-;   add t4, s2, t4
+;   sd t4, 0x430(sp)
-;   ld s9, 0x478(sp)
+;   addi t4, s7, 0x1d
-;   ld s7, 0x480(sp)
+;   sd t4, 0x428(sp)
-;   add s6, s7, s9
+;   addi t4, s8, 0x1f
-;   ld s3, 0x468(sp)
+;   sd t4, 0x420(sp)
-;   ld s1, 0x470(sp)
+;   addi t4, s9, 0x21
-;   add s7, s1, s3
+;   sd t4, 0x418(sp)
-;   ld s8, 0x458(sp)
+;   addi t4, s10, 0x23
-;   ld s9, 0x460(sp)
+;   sd t4, 0x410(sp)
-;   add s8, s9, s8
+;   addi t4, s11, 0x25
-;   ld s2, 0x448(sp)
+;   sd t4, 0x408(sp)
-;   ld s11, 0x450(sp)
+;   addi t4, s1, 0x27
-;   add s9, s11, s2
+;   sd t4, 0x400(sp)
-;   ld s10, 0x438(sp)
+;   addi t4, s2, 0x1f
-;   ld s11, 0x440(sp)
+;   sd t4, 0x3f8(sp)
-;   add s10, s11, s10
+;   addi t4, s3, 0x21
-;   ld s1, 0x428(sp)
+;   sd t4, 0x3f0(sp)
+;   addi s4, s4, 0x23
+;   addi a0, a0, 0x25
+;   ld t4, 0x4e8(sp)
+;   addi t4, t4, 0x27
+;   ld t3, 0x4e0(sp)
+;   addi t0, t3, 0x1f
+;   ld t1, 0x4d8(sp)
+;   addi t1, t1, 0x21
+;   ld a1, 0x4d0(sp)
+;   addi t2, a1, 0x23
+;   ld a4, 0x4c8(sp)
+;   addi a1, a4, 0x25
+;   ld a7, 0x4c0(sp)
+;   addi a2, a7, 0x27
+;   ld a3, 0x4b8(sp)
+;   addi a3, a3, 0x1f
+;   ld a4, 0x4b0(sp)
+;   addi a4, a4, 0x21
+;   ld a5, 0x4a8(sp)
+;   addi a5, a5, 0x23
+;   ld a6, 0x4a0(sp)
+;   addi a6, a6, 0x25
+;   ld a7, 0x498(sp)
+;   addi a7, a7, 0x27
+;   ld t3, 0x488(sp)
+;   ld s11, 0x490(sp)
+;   add t3, s11, t3
+;   ld s7, 0x478(sp)
+;   ld s5, 0x480(sp)
+;   add s5, s5, s7
+;   ld s1, 0x468(sp)
+;   ld s10, 0x470(sp)
+;   add s6, s10, s1
+;   ld s7, 0x458(sp)
+;   ld s8, 0x460(sp)
+;   add s7, s8, s7
+;   ld s11, 0x448(sp)
+;   ld s9, 0x450(sp)
+;   add s8, s9, s11
+;   ld s9, 0x438(sp)
+;   ld s3, 0x440(sp)
+;   add s9, s3, s9
+;   ld s10, 0x428(sp)
 ;   ld s11, 0x430(sp)
-;   add s11, s11, s1
+;   add s10, s11, s10
-;   ld s1, 0x418(sp)
+;   ld s11, 0x418(sp)
-;   ld s4, 0x420(sp)
+;   ld s2, 0x420(sp)
-;   add s1, s4, s1
+;   add s11, s2, s11
-;   ld s2, 0x408(sp)
+;   ld s1, 0x408(sp)
-;   ld s3, 0x410(sp)
+;   ld s2, 0x410(sp)
-;   add s2, s3, s2
+;   add s1, s2, s1
-;   ld s4, 0x3f8(sp)
+;   ld s3, 0x3f8(sp)
-;   ld s3, 0x400(sp)
+;   ld s2, 0x400(sp)
+;   add s2, s2, s3
+;   ld s3, 0x3f0(sp)
 ;   add s3, s3, s4
-;   ld s4, 0x3f0(sp)
+;   add t4, a0, t4
-;   add s5, s4, s5
+;   add t0, t0, t1
-;   add t0, a0, t0
+;   add t1, t2, a1
-;   add t1, t1, t2
+;   add t2, a2, a3
+;   add a0, a4, a5
+;   add a1, a6, a7
+;   add a2, t3, s5
+;   add a3, s6, s7
+;   add a4, s8, s9
+;   add a5, s10, s11
+;   add a6, s1, s2
+;   add t4, s3, t4
+;   add t0, t0, t1
+;   add t1, t2, a0
 ;   add t2, a1, a2
 ;   add a0, a3, a4
 ;   add a1, a5, a6
-;   add a2, a7, t3
+;   add t4, t4, t0
-;   add t4, t4, s6
+;   add t0, t1, t2
-;   add a3, s7, s8
-;   add a4, s9, s10
-;   add a5, s11, s1
-;   add a6, s2, s3
-;   add t0, s5, t0
-;   add t1, t1, t2
-;   add t2, a0, a1
-;   add t4, a2, t4
-;   add a0, a3, a4
-;   add a1, a5, a6
-;   add t0, t0, t1
-;   add t4, t2, t4
 ;   add t1, a0, a1
-;   add t4, t0, t4
+;   add t4, t4, t0
 ;   add a1, t1, t4
 ;   ld a0, 0x3e8(sp)
-;   addi sp, sp, 0x500
+;   addi sp, sp, 0x550
 ;   ld s1, -8(sp)
 ;   ld s2, -0x10(sp)
 ;   ld s3, -0x18(sp)