Commit Graph

51 Commits

Author SHA1 Message Date
Andrew Brown
af1499ce99 Add x86 implementation of shuffle 2019-09-19 10:53:40 -07:00
julian-seward1
9e088e4164 Reorganise optimisation level settings, and make the insn shrink pass optional (#1044)
This patch:

* removes the "default" opt level, on the basis that it has no definition and
  is referred to nowhere in the compiler.

* renames the "fastest" level to "none".  The resulting set of transformations
  is unchanged.

* renames the "best" level to "speed_and_size".  The resulting set of
  transformations is unchanged.

* adds a new level, "speed".  This is the same as "speed_and_size" except that
  it omits transformations aimed only at reducing code size.  Currently it
  omits only the insn shrinking pass.
2019-09-19 18:51:25 +02:00
bjorn3
add6a4f269 Correctly zero extend operand of fcvt_from_uint for 8ints and 16bit ints (#997)
Fixes #996
2019-09-18 10:06:15 +02:00
Ujjwal Sharma
3418fb6e18 [codegen] reintroduce support for carry and borrow instructions in RI… (#1005)
Reintroduce support for iadd carry variants and isub borrow variants for
RISC ISAs which had been removed in
https://github.com/CraneStation/cranelift/pull/961 and
https://github.com/CraneStation/cranelift/pull/962 because of the lack
of a proper flags register in RISC architectures.
2019-09-13 17:27:49 +02:00
Benjamin Bouvier
3aa76b558c Legalize i64.const by breaking it into two i32.const, on 32-bits platforms; 2019-09-10 19:50:34 +02:00
Andrew Brown
6f1ed94e82 Fix documentation 2019-09-10 10:45:12 -07:00
bjorn3
0273eb84e0 Fix rebase 2019-09-07 09:55:09 -07:00
bjorn3
67593d997b Add b128 type to fix tests 2019-09-07 09:55:09 -07:00
bjorn3
fa9602df80 Legalize load.i128 and store.i128 2019-09-07 09:55:09 -07:00
bjorn3
0d5b87038a Rustfmt 2019-09-07 09:55:09 -07:00
bjorn3
599b48d95f Narrowing legalize some more bitops 2019-09-07 09:55:09 -07:00
bjorn3
762b5e494b Legalize brz.i128 and brnz.i128 2019-09-07 09:55:09 -07:00
bjorn3
c9a25abbc4 Basic i128 support 2019-09-07 09:55:09 -07:00
Benjamin Bouvier
c1609b70e8 [codegen] Allow using the pinned register as the heap base via a setting; 2019-09-06 16:18:27 +02:00
Benjamin Bouvier
660b8b28b8 [codegen] Add a pinned register that's entirely under the control of the user; 2019-09-06 16:18:27 +02:00
Benjamin Bouvier
d1d2e790b9 [meta] Morph a few pub into pub(crate), and remove dead code; 2019-09-06 15:47:20 +02:00
Benjamin Bouvier
8fba449b7b [meta] Introduce the EntityRefs structure instead of using dynamic lookup; 2019-09-06 15:47:20 +02:00
Benjamin Bouvier
29e3ec51c1 [meta] Introduce the Immediates structure instead of using dynamic lookup; 2019-09-06 15:47:20 +02:00
Ujjwal Sharma
1a099f2e8c [codegen] change operand type from bool to iflag for isub borrow variants
The type of the borrow operands for the borrow variants of the isub
instruction (isub_bin, isub_bout, isub_borrow) was bool for compatibility
reasons for isa/riscv. Since support for these instructions on RISC
architectures has been temporarily suspended, we can safely change the
type to iflags.
2019-09-05 19:28:33 +02:00
Ujjwal Sharma
9fb8bdd6d5 [codegen] remove support for isub borrow variants on riscv
Previously, the borrow variants of isub (isub_bin, isub_bout and
isub_borrow) were being legalized for isa/riscv since RISC architectures
lack a flags register.

This forced us to return and accept booleans for these operations, which
proved to be problematic and inconvenient, especially for x86.

This commit removes support for said statements and all dependent
statements for isa/riscv so that we can work on a better legalization
strategy in the future.
2019-09-05 19:28:33 +02:00
Benjamin Bouvier
0acddc08ea [meta] Split FormatBuilder::imm to avoid the extra Into<> parameter type; 2019-09-05 17:55:03 +02:00
Ujjwal Sharma
ea919489ee [codegen] add encodings for iadd carry variants (#961)
* [codegen] add encodings for iadd carry variants

Add encodings for iadd carry variants (iadd_cout, iadd_cin, iadd_carry)
for x86_32, enabling the legalization for iadd.i64 to work.

* [codegen] remove support for iadd carry variants on riscv

Previously, the carry variants of iadd (iadd_cin, iadd_cout and
iadd_carry) were being legalized for isa/riscv since RISC architectures
lack a flags register.

This forced us to return and accept booleans for these operations, which
proved to be problematic and inconvenient, especially for x86.

This commit removes support for said statements and all dependent
statements for isa/riscv so that we can work on a better legalization
strategy in the future.

* [codegen] change operand type from bool to iflag for iadd carry variants

The type of the carry operands for the carry variants of the iadd
instruction (iadd_cin, iadd_cout, iadd_carry) was bool for compatibility
reasons for isa/riscv. Since support for these instructions on RISC
architectures has been temporarily suspended, we can safely change the
type to iflags.
2019-09-05 15:03:13 +02:00
Benjamin Bouvier
49a37e48fb [codegen] Make scalar_to_vector's output type a lane of its input type; 2019-09-04 19:09:54 +02:00
Andrew Brown
407d24c013 Add operand kind and format for unsigned 128-bit immediates 2019-08-26 16:12:06 -07:00
julian-seward1
b8fb52446c Cranelift: implement redundant fill removal on tree-shaped CFG regions. Mozilla bug 1570584. (#906) 2019-08-25 19:37:34 +02:00
Carmen Kwan
19257f80c1 Add reference types R32 and R64
-Add resumable_trap, safepoint, isnull, and null instructions
-Add Stackmap struct and StackmapSink trait

Co-authored-by: Mir Ahmed <mirahmed753@gmail.com>
Co-authored-by: Dan Gohman <sunfish@mozilla.com>
2019-08-16 11:35:16 -07:00
Benjamin Bouvier
2ee35b7ea1 Implement a Windows Baldrdash calling convention; 2019-08-16 14:25:15 +02:00
Benjamin Bouvier
d8d3602257 Adds the libcall_call_conv setting and use it for libcall calls expansion; 2019-08-12 16:12:00 -07:00
Benjamin Bouvier
627ba24b59 Simplify jump table instructions and add missing conversion;
This makes non-legalized jump table instructions operate on operands with
pointer-sized types. This means we need to extend smaller types into the
pointer-sized operand, when the two don't match.
2019-08-02 18:39:39 +02:00
Andrew Brown
61772e9775 Add raw_bitcast instruction
Casts bits as a different type of the same width with no change to the data (unlike bitcast)
2019-07-16 17:07:44 -07:00
Andrew Brown
5f0e5567c1 Add scalar_to_vector instruction
Moves scalar values in a GPR register to an FPR register
2019-07-16 17:07:44 -07:00
Andrew Brown
f2c48009e8 Disable SIMD features by default 2019-07-16 17:07:44 -07:00
Benjamin Bouvier
bfc1468688 [docs] Don't accidentally generate doc tests; 2019-07-11 11:48:45 +02:00
Benjamin Bouvier
062ed8f6ea [docs] Remove rst annotations in instructions doc comments; 2019-07-11 11:48:45 +02:00
Benjamin Bouvier
21aaf0c89f [meta] Add cdsl facilities for encodings and recipes;
Co-authored-by: Benjamin Bouvier <public@benj.me>
Co-authored-by: bjorn3 <bjorn3@users.noreply.github.com>
2019-07-05 11:38:51 +02:00
Benjamin Bouvier
f1d1d1e960 [meta] Uniquely number every instruction in the Rust crate; 2019-07-03 18:39:28 +02:00
Benjamin Bouvier
83336290c2 Mark the jump_table_entry Instruction as loading; 2019-06-27 17:38:20 +02:00
Benjamin Bouvier
70f79d23bf [meta] Make Builders build() instead of finish(); 2019-05-29 14:05:01 +02:00
Benjamin Bouvier
d9277f249b [meta] Introduce the InstructionGroupBuilder;
This follows the rest of the code base data structures, where we have a
mutable data structure builder; once the data structure is constructed,
it's immutable.

This also makes the definition of instructions easier, and it paves the
way for defining immediate variants.
2019-05-29 14:05:01 +02:00
Benjamin Bouvier
22a6823496 [meta] Rename cdsl/inst to cdsl/instructions; 2019-05-29 14:05:01 +02:00
Julian Seward
03368895fe Cranelift: Redundant stack-slot-to-stack-slot copy removal. PR#773.
This is also https://bugzilla.mozilla.org/show_bug.cgi?id=1552737.

Cranelift currently has a tendency to create redundant copies (self-copies) of
values from a stack slot back to the same stack slot.  This generates a
pointless load and store and an unnecessary register use.  The copies are
created by `visit_inst` in regalloc/reload.rs.  They appear to occur mostly,
but not exclusively, at loop heads.  It's unclear why this happens.

This patch adds a special case to `visit_inst` to find such copies.  They are
converted into a new instruction, `copy_nop`, which takes and produces the
same SSA names, so as not to break any of the SSA invariants, but which has a
zero-length encoding, hence removing the copy at emission time.

`copy_nop`s source and destination operands must be stack slots and of course
the *same* stack slot.  The verifier has been enhanced to check this, since
misuse of `copy_nop` will likely lead to hard-to-find incorrect-code bugs.

Attempts were made to write a standalone .clif test case.  But these failed
because it appears the .clif parser accepts but ignores location hints that
are stack slots.  So it's impossible to write, in clif, the exact form of
`copy` instruction that triggers the transformation.
2019-05-27 13:55:48 +02:00
Benjamin Bouvier
6935033c9e [meta] Have bind() be a method of {Bound,}Instruction instead of a static method; 2019-05-23 14:31:00 +02:00
Benjamin Bouvier
a46b2d7173 [meta] Move ApplyTarget/bind to cdsl/inst; 2019-05-23 14:31:00 +02:00
Benjamin Bouvier
97ebaa6f37 Add Rust implementation and address review comments of #742; 2019-05-20 11:52:43 +02:00
Benjamin Bouvier
d00e42ede3 [meta] Port shared and x86 legalizations to the Rust crate; 2019-04-25 11:44:56 +02:00
Benjamin Bouvier
b3a950b589 [meta] Fix condition codes in immediates; 2019-04-24 10:47:26 +02:00
Benjamin Bouvier
6053201128 [meta] Move the TypeSet building out of the TypeVar builder so as to test it; 2019-04-02 17:30:50 +02:00
Benjamin Bouvier
86430abc4c [meta] Port all the Cranelift instructions to the meta crate; 2019-03-28 14:13:29 +01:00
Benjamin Bouvier
d59bef1902 [meta] Port Formats and Operands to the Rust crate; 2019-03-27 14:43:27 +01:00
Benjamin Bouvier
f3f449b45b [meta] Tweak generation of settings/registers; 2019-03-27 14:43:27 +01:00