Commit Graph

91 Commits

Author SHA1 Message Date
Andrew Brown
fa7481a681 Add x86 implementation of SIMD swizzle instruction 2020-03-06 15:49:53 -08:00
Andrew Brown
6e0401b83a Refactor SIMD lane instructions to separate define* function 2020-03-06 14:57:11 -08:00
bjorn3
0a1bb3ba6c Add TLS support for ELF and MachO (#1174)
* Add TLS support
* Add binemit and legalize tests
* Spill all caller-saved registers when necessary
2020-02-25 17:50:04 -08:00
Andrew Brown
032e81fd6f Add x86 SIMD average rounding 2020-02-24 09:48:38 -08:00
Andrew Brown
3ae1af1ad2 Add new Cranelift instructions for integer min/max
This includes legalizations to the previously-existing x86 SIMD integer min/max.
2020-02-21 09:33:43 -08:00
Ryan Hunt
832666c45e Mass rename Ebb and relatives to Block (#1365)
* Manually rename BasicBlock to BlockPredecessor

BasicBlock is a pair of (Ebb, Inst) that is used to represent the
basic block subcomponent of an Ebb that is a predecessor to an Ebb.

Eventually we will be able to remove this struct, but for now it
makes sense to give it a non-conflicting name so that we can start
to transition Ebb to represent a basic block.

I have not updated any comments that refer to BasicBlock, as
eventually we will remove BlockPredecessor and replace with Block,
which is a basic block, so the comments will become correct.

* Manually rename SSABuilder block types to avoid conflict

SSABuilder has its own Block and BlockData types. These along with
associated identifier will cause conflicts in a later commit, so
they are renamed to be more verbose here.

* Automatically rename 'Ebb' to 'Block' in *.rs

* Automatically rename 'EBB' to 'block' in *.rs

* Automatically rename 'ebb' to 'block' in *.rs

* Automatically rename 'extended basic block' to 'basic block' in *.rs

* Automatically rename 'an basic block' to 'a basic block' in *.rs

* Manually update comment for `Block`

`Block`'s wikipedia article required an update.

* Automatically rename 'an `Block`' to 'a `Block`' in *.rs

* Automatically rename 'extended_basic_block' to 'basic_block' in *.rs

* Automatically rename 'ebb' to 'block' in *.clif

* Manually rename clif constant that contains 'ebb' as substring to avoid conflict

* Automatically rename filecheck uses of 'EBB' to 'BB'

'regex: EBB' -> 'regex: BB'
'$EBB' -> '$BB'

* Automatically rename 'EBB' 'Ebb' to 'block' in *.clif

* Automatically rename 'an block' to 'a block' in *.clif

* Fix broken testcase when function name length increases

Test function names are limited to 16 characters. This causes
the new longer name to be truncated and fail a filecheck test. An
outdated comment was also fixed.
2020-02-07 10:46:47 -06:00
Ryan Hunt
bbc0a328c7 Codegen: Allow encoding of (r32|r64).(load|store)
Accessing Wasm reference globals that are reference types will
want to use the plain load/store instructions. This commit adds
encodings for these instructions to match loading a i32/i64.
Producers of IR are required to insert the appropriate barriers
around the loads/stores.
2020-01-23 13:37:11 -06:00
Ryan Hunt
848baa0aa7 Codegen: Add ref.is_invalid instruction
Spidermonkey returns a sentinel ref value of '-1' from some VM functions
to indicate failure. This commit adds an instruction analagous to ref.is_null
that checks for this value.
2020-01-23 13:37:11 -06:00
Benjamin Bouvier
dd497c19e1 Renames Settings ⚠️ (fixes #976) (#1321)
This is a breaking API change: the following settings have been renamed:

- jump_tables_enabled -> enable_jump_tables
- colocated_libcalls -> use_colocated_libcalls
- probestack_enabled -> enable_probestack
- allones_funcaddrs -> emit_all_ones_funcaddrs
2020-01-13 14:42:49 -07:00
Benjamin Bouvier
3a4b1cc989 Split define encodings + start splitting instruction definitions (#1322)
* [meta] Split the x86 encodings define function into smaller ones;
* [meta] Start splitting instruction definitions into smaller functions;
2020-01-08 09:38:40 -08:00
bjorn3
4cc0241f37 More i8 legalizations (#1253)
* Legalize stack_{load,store}.i8, fixes #433
* Legalize select.i8, cc: #466
* Legalize brz.i8 and brnz.i8, cc: #1117
2019-12-04 09:16:22 -08:00
Mike Hommey
b342cbdd64 Sort the list of instruction formats by name
This makes opcodes.rs and inst_builders.rs deterministic.
2019-12-04 12:15:48 +01:00
Benjamin Bouvier
de7c0dddc6 Fix #1247: Tweak enable_verifier doc comment so it's true 2019-12-04 09:42:55 +01:00
krk
bc9f05e5e2 Add legalization for bitrev.i128 via narrowing, fixes #1116 (#1229) 2019-11-22 12:38:04 +01:00
bjorn3
c5e74986e1 Legalize uextend and sextend to 128bit ints 2019-11-19 14:42:21 -08:00
krk
f7c7245b06 Add legalization for popcnt.i128 via narrowing, fixes #1116 2019-11-15 14:03:49 +01:00
Benjamin Bouvier
d8b840d2f5 [meta] Remove the OperandKindBuilder;
And replace it by constructors in OperandKind. There's a single optional
parameter function `set_doc` that remains, and didn't justify the whole
OperandKindBuilder concept to exist.
2019-10-30 18:39:20 +01:00
Benjamin Bouvier
d5e990220e [meta] Remove OperandKind::name field and explicitly pass rust_field_name/rust_type; (fixes #1177) 2019-10-30 18:39:20 +01:00
Benjamin Bouvier
0eb2dfc4a3 [meta] Rename OperandKind::default_member to format_field_name; 2019-10-30 18:39:20 +01:00
Benjamin Bouvier
4632d35196 [meta] Remove the OperandBuilder, replace it with Operand ctors; 2019-10-30 18:39:20 +01:00
Benjamin Bouvier
5889dd2c64 [meta] Add more pub(crate) definitions. 2019-10-29 14:23:10 +01:00
Peter Huene
9f506692c2 Fix clippy warnings.
This commit fixes the current set of (stable) clippy warnings in the repo.
2019-10-24 17:20:12 -07:00
Andrew Brown
879ccf871a Add x86 SIMD vall_true
In order to implement SIMD's all_true (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#all-lanes-true), we must legalize some instruction (I chose `vall_true`) to a comparison against 0 and a similar reduction as vany_true using `PTEST` and `SETNZ`. Since `icmp` only allows integers but `vall_true` could allow more vector types, `raw_bitcast` is used to convert the lane types into integers, e.g. b32x4 to i32x4. To do so without runtime type-checking, the `raw_bitcast` instruction (which emits no instruction) can now bitcast from any vector type to the same type, e.g. i32x4 to i32x4.
2019-10-22 11:01:05 -07:00
Andrew Brown
186effc420 Add x86 SIMD vany_true and x86_ptest
In order to implement SIMD's any_true (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#any-lane-true), we must legalize some instruction (I chose `vany_true`) to a sequence of `PTEST` and `SETNZ`. To emit `PTEST` I added the new CLIF instruction `x86_ptest` and used CLIF's `trueif ne` for `SETNZ`.
2019-10-22 11:01:05 -07:00
Benjamin Bouvier
0243b642e3 [meta] Remove name lookups in formats;
This does a lot at once, since there was no clear way to split the three
commits:

- Instruction need to be passed an explicit InstructionFormat,
- InstructionFormat deduplication is checked once all entities have been
defined;
2019-10-22 14:05:12 +02:00
Benjamin Bouvier
d3e694fbe7 [meta] Remove unused InstructionGroup::{name, doc}; 2019-10-22 14:05:12 +02:00
Andrew Brown
b927c55511 Add SIMD bitselect instruction and x86 legalization
This new instructions matches the `bitselect` behavior described in the WASM SIMD spec (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#bitwise-select)
2019-10-17 15:49:29 -07:00
Andrew Brown
6d690e5275 Allow binding immediates to instructions (#1012)
This change should make the code more clear (and less code) when adding encodings for instructions with specific immediates; e.g., a constant with a 0 immediate could be encoded as an XOR with something like `const.bind(...)` without explicitly creating the necessary predicates. It has several parts:
* Introduce Bindable trait to instructions
* Convert all instruction bindings to use Bindable::bind()
* Add ability to bind immediates to BoundInstruction
This is an attempt to reduce some of the issues in #955.
2019-10-10 08:54:46 -07:00
Ujjwal Sharma
f1c25c2c5a [codegen] legalize imul for 64-bit and 128-bit operands
Add a legalization that legalizes imul.I64 for 32-bit ISAs and imul.I128
for 64-bit (and subsequently 32-bit) ISAs.

Refs: https://github.com/bnjbvr/cranelift-x86/issues/4
2019-10-10 17:39:40 +02:00
Ujjwal Sharma
c062f12d7c [codegen] legalize icmp for 64 and 128 bit operands
Add legalizations for icmp and icmp_imm for i64 and i128 operands for
the narrow legalization set, allowing 32-bit ISAs (like x86-32) to
compare 64-bit integers and all ISAs to compare 128-bit integers.

Fixes: https://github.com/bnjbvr/cranelift-x86/issues/2
2019-10-10 11:06:19 +02:00
bjorn3
093b3b3426 Fix brz.i128
Fixes #1066
2019-10-02 11:04:29 +02:00
Andrew Brown
90c49a2f7c Add saturating subtraction with a SIMD encoding
This includes the new instructions `ssub_sat` and `usub_sat` and only encodes the i8x16 and i16x8 types; these are what is needed for implementing the SIMD spec (see https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#saturating-integer-subtraction).
2019-09-30 13:54:30 -07:00
Andrew Brown
21144068d4 Add saturating addition with a SIMD encoding
This includes the new instructions `sadd_sat` and `uadd_sat` and only encodes the i8x16 and i16x8 types; these are what is needed for implementing the SIMD spec (see https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#saturating-integer-addition).
2019-09-30 13:54:30 -07:00
Andrew Brown
630cb3ee62 Add x86 encoding for SIMD imul
Only i16x8 and i32x4 are encoded in this commit mainly because i8x16 and i64x2 do not have simple encodings in x86. i64x2 is not required by the SIMD spec and there is discussion (https://github.com/WebAssembly/simd/pull/98#issuecomment-530092217) about removing i8x16.
2019-09-30 13:54:30 -07:00
Andrew Brown
ba393afd4d Add x86 legalization for SIMD ineg 2019-09-30 13:54:30 -07:00
Ujjwal Sharma
9f3c5b967e [codegen] add documentation for overflow
Add documentation to the icmp instruction text for both signed and
unsigned overflow, making it very clear why unsigned overflow is
complicated and where to find it.
2019-09-27 16:29:16 -07:00
Ujjwal Sharma
43a891dfa2 [codegen] add intcc conditions for reading overflow flag
Add conditions to IntCC for checking the overflow flag (Overflow,
NotOverflow).
2019-09-25 11:42:58 +02:00
Ujjwal Sharma
6e131e5347 [codegen] add intcc conditions for reading carry flag
Add conditions to IntCC for checking the carry flag (Carry, NotCarry).

Fixes: https://github.com/CraneStation/cranelift/issues/980
2019-09-24 15:12:09 -07:00
Nicolas B. Pierron
694de912a5 Update brnz.i128 legalization to use non-extended basic blocks. 2019-09-24 15:55:58 +02:00
Nick Fitzgerald
9b8e7b511e tidy: Remove extra semicolons
These were causing compilation warnings.
2019-09-19 16:25:49 -07:00
Andrew Brown
af1499ce99 Add x86 implementation of shuffle 2019-09-19 10:53:40 -07:00
julian-seward1
9e088e4164 Reorganise optimisation level settings, and make the insn shrink pass optional (#1044)
This patch:

* removes the "default" opt level, on the basis that it has no definition and
  is referred to nowhere in the compiler.

* renames the "fastest" level to "none".  The resulting set of transformations
  is unchanged.

* renames the "best" level to "speed_and_size".  The resulting set of
  transformations is unchanged.

* adds a new level, "speed".  This is the same as "speed_and_size" except that
  it omits transformations aimed only at reducing code size.  Currently it
  omits only the insn shrinking pass.
2019-09-19 18:51:25 +02:00
bjorn3
add6a4f269 Correctly zero extend operand of fcvt_from_uint for 8ints and 16bit ints (#997)
Fixes #996
2019-09-18 10:06:15 +02:00
Ujjwal Sharma
3418fb6e18 [codegen] reintroduce support for carry and borrow instructions in RI… (#1005)
Reintroduce support for iadd carry variants and isub borrow variants for
RISC ISAs which had been removed in
https://github.com/CraneStation/cranelift/pull/961 and
https://github.com/CraneStation/cranelift/pull/962 because of the lack
of a proper flags register in RISC architectures.
2019-09-13 17:27:49 +02:00
Benjamin Bouvier
3aa76b558c Legalize i64.const by breaking it into two i32.const, on 32-bits platforms; 2019-09-10 19:50:34 +02:00
Andrew Brown
6f1ed94e82 Fix documentation 2019-09-10 10:45:12 -07:00
bjorn3
0273eb84e0 Fix rebase 2019-09-07 09:55:09 -07:00
bjorn3
67593d997b Add b128 type to fix tests 2019-09-07 09:55:09 -07:00
bjorn3
fa9602df80 Legalize load.i128 and store.i128 2019-09-07 09:55:09 -07:00
bjorn3
0d5b87038a Rustfmt 2019-09-07 09:55:09 -07:00