Jakob Stoklund Olesen
fd58b7cc29
Add vsplit and vconcat instructions.
...
Add support for two new type variable functions: half_vector() and
double_vector().
Use these two instructions to break down unsupported SIMD types and
build them up again.
2017-03-07 14:31:57 -08:00
Angus Holder
855c429d31
Documentation fix for what appears to be a minor copy-paste mistake.
2017-02-22 09:33:17 -08:00
Jakob Stoklund Olesen
b6fa40d6a3
Add a return_reg instruction to the base instruction set.
...
Register-style return is used by all RISC architectures, so it is
natural to have a shared instruction representation.
2017-02-21 13:05:17 -08:00
Dominik Inführ
8285f2a672
added Opcode flags methods
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generate `is_branch`, `is_terminator`, `can_trap` methods for `enum
Opcode`.
2016-12-02 15:50:28 -08:00
Jakob Stoklund Olesen
0b9b956695
Split out instruction definitions.
...
- cdsl.instructions defines the Instruction class.
- base.instructions defines the base instruction set.
2016-11-08 12:33:50 -08:00
