wasmtime

T0b1/wasmtime

Fork 0

Commit Graph

Author	SHA1	Message	Date
Jakob Stoklund Olesen	fb4db38dd6	Fill in boilerplate for Intel and ARM targets. The intel, arm32, and arm32 targets were only defined in the meta language previously. Add Rust implementations too. This is mostly boilerplate, except for the unit tests in the registers.rs files.	2016-11-23 10:42:07 -08:00
Jakob Stoklund Olesen	060735adfe	Define register classes for 4 ISAs.	2016-11-11 15:08:12 -08:00
Jakob Stoklund Olesen	e1c0171b2c	Define register banks. Add a RegBank class for describing CPU register banks. Define register banks for all the ISA stubs. The ARM32 floating point bank in particular requires attention.	2016-11-11 14:17:10 -08:00

Author

SHA1

Message

Date

Jakob Stoklund Olesen

fb4db38dd6

Fill in boilerplate for Intel and ARM targets.

The intel, arm32, and arm32 targets were only defined in the meta
language previously. Add Rust implementations too.

This is mostly boilerplate, except for the unit tests in the
registers.rs files.

2016-11-23 10:42:07 -08:00

Jakob Stoklund Olesen

060735adfe

Define register classes for 4 ISAs.

2016-11-11 15:08:12 -08:00

Jakob Stoklund Olesen

e1c0171b2c

Define register banks.

Add a RegBank class for describing CPU register banks.

Define register banks for all the ISA stubs. The ARM32 floating point
bank in particular requires attention.

2016-11-11 14:17:10 -08:00

3 Commits