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4 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
aa7e349134 Add a section about implementation limits. 
Fix a few other minor issues with the documentation.
 2017-02-24 11:08:15 -08:00
Jakob Stoklund Olesen
fb4db38dd6 Fill in boilerplate for Intel and ARM targets. 
The intel, arm32, and arm32 targets were only defined in the meta
language previously. Add Rust implementations too.

This is mostly boilerplate, except for the unit tests in the
registers.rs files.
 2016-11-23 10:42:07 -08:00
Jakob Stoklund Olesen
353caf23cd Generate register bank descriptions. 
Use the information in the ISA's registers.py files to generate a
RegInfo Rust data structure.
 2016-11-22 18:15:21 -08:00
Jakob Stoklund Olesen
34f7b93482 Add stubs for Intel and ARM architectures. 
The Intel ISA handles both 32-bit and 64-bit code.

ARM is split into separate arm32 and arm64 ISAs since the architectures
have little in common in instruction encodings and register files.
 2016-11-11 11:32:05 -08:00