It was the caller's responsibility to call TargetIsa::check() before;
now one can't manipulate a TargetIsa without calling the
TargetIsaBuilder::finish() method, which is less error-prone and more in
line with what's coming for other things we're going to generate in the
meta crate.
Also splits the construction of a RegClass in two parts: a prototype is
made first when declaring the RegClass, and missing bits are filled in
when adding it to the TargetIsa(Builder). This avoids an awkward passing
of the isa to the RegClass ctor.
It appears that having the meta directory crate be inside the codegen
directory is not enough to allow codegen to depend on it without it
being published. So, let's just publish it.
- don't generate "&& true" when generating instruction eq() fn;
- use more Self;
- use subsec_millis instead of subsec_nanos and divide;
- coalesce two ifs;
* Don't implement Eq and Hash for EntityList
* Generate eq and hash methods for InstructionData
* Use the eq() and hash() methods of InstructionData in simple_gvn
The documentation for these instructions suggests that immediate values
which could lead to trapping should be invalid.
While it seems nice to have these instructions be always non-trapping,
it's also nice to say that the `_imm` forms of instructions are
interchangeable with the corresponding non-`_imm` forms accompanied
by `iconst` instructions.
This requires splitting X86PCRel4 into two separate relocations, to
distinguish the case where the instruction is a call, as Mach-O uses a
different relocation in that case.
This also makes it explicit that only x86-64 relocations are supported
currently.
`urm_noflags` is a variant of `urm` which doesn't clobber the flags, and
`urm_noflags_abcd` is a further variant for ABCD registers, so it also
doesn't clobber the flags.
This switches from a custom list of architectures to use the
target-lexicon crate.
- "set is_64bit=1; isa x86" is replaced with "target x86_64", and
similar for other architectures, and the `is_64bit` flag is removed
entirely.
- The `is_compressed` flag is removed too; it's no longer being used to
control REX prefixes on x86-64, ARM and Thumb are separate
architectures in target-lexicon, and we can figure out how to
select RISC-V compressed encodings when we're ready.
* Optimize 0.0 floating point constants. Rather than using the existing
process of emitting bit patterns and moving them into floating point
registers, use the `xorps` instruction to zero out the register.
* is_zero predicate function will not accept negative zero. Fixed formatting for encoding recipe and filetests.
