Commit Graph

930 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
f4929825ca Add subtract and logical instruction encodings to Intel-32.
Also add versions with 8-bit and 32-bit immediate operands.
2017-05-12 15:37:12 -07:00
Jakob Stoklund Olesen
c713ea8c57 Add fixed constraints for ABI arguments and return values.
We can start adding some real test cases for the move resolver now.
2017-05-11 12:02:02 -07:00
Jakob Stoklund Olesen
d1390006b1 Always create live ranges for dead EBB arguments.
The live value tracker expects them to be there.

We may eventually delete dead arguments from internal EBBs, but at least
the entry block needs to be able to handle dead function arguments.
2017-05-11 11:42:44 -07:00
Jakob Stoklund Olesen
a0085434af Add encodings for Intel dynamic shift instructions.
These instructions have a fixed register constraint; the shift amount is
passed in CL.

Add meta language syntax so a fixed register can be specified as
"GPR.rcx".
2017-05-09 13:11:50 -07:00
Jakob Stoklund Olesen
041fda63ac Add the very basics of Intel 32-bit instruction encodings.
Tabulate the Intel opcode representations and implement an OP() function
which computes the encoding bits.

Implement the single-byte opcode with a reg-reg ModR/M byte.
2017-05-08 16:57:38 -07:00
Jakob Stoklund Olesen
950838c489 Add a regmove instruction.
This will be used to locally change the register locations of values in
order to satisfy instruction constraints.
2017-05-02 11:32:12 -07:00
Jakob Stoklund Olesen
eaf1ed09fc Color entry block arguments using the function signature.
The arguments to the entry block arrive in registers determined by the
ABI. This information is stored in the signature.

Use a separate function for coloring entry block arguments using the
signature information. We can't handle stack arguments yet.
2017-04-26 14:38:16 -07:00
Jakob Stoklund Olesen
6197bfff72 Add a TargetIsa::allocatable_registers() method.
This gives the target ISA a chance to reserve registers like the stack
pointer or hard-wired 0 registers like %x0 on RISC-V.
2017-04-26 13:54:40 -07:00
Jakob Stoklund Olesen
a4acc26d5a Add an enable_e setting for the RV32E instruction set.
This limited RISC-V version only has registers %x0 - %x15.

Make sure the ABI lowering code doesn't use the banned registers for
arguments.
2017-04-26 13:50:52 -07:00
Eric Anholt
43ce26e64b Verify that the instruction encoding matches what the ISA would encode.
Fixes #69
2017-04-23 17:21:32 -07:00
Jakob Stoklund Olesen
d66a9d196e Implement binary emission of RISC-V return instructions.
The return address is now always supplied in %x1, so the return address
predictor will recognize the jalr as a return and not some indirect
branch.
2017-04-19 16:26:04 -07:00
Jakob Stoklund Olesen
0cb36c9031 Remove the return_reg instruction.
RISC architectures that take a return address in a register can use a
special-purpose `link` return value to do so.
2017-04-19 16:08:16 -07:00
Jakob Stoklund Olesen
e44a5a4391 Append link and sret arguments in legalize_signature.
These special-purpose arguments and return values are only relevant for
the function being compiled, so add a `current` flag to
legalize_signature().

- Add the necessary argument values to the entry block to represent
  the special-purpose arguments.
- Propagate the link and sret arguments to return instructions if the
  legalized signature asks for it.
2017-04-19 15:55:12 -07:00
Jakob Stoklund Olesen
49c1209572 Fix broken test. 2017-04-17 15:45:55 -07:00
Jakob Stoklund Olesen
d424589daa Allow for special purpose function arguments and return values.
Enumerate a set of special purposes for function arguments that general
purpose code needs to know about. Some of these argument purposes will
only appear in the signature of the current function, representing
things the prologue and epilogues need to know about like the link
register and callee-saved registers.

Get rid of the 'inreg' argument flag. Arguments can be pre-assigned to a
specific register instead.
2017-04-17 15:06:30 -07:00
Jakob Stoklund Olesen
3c8bdba15e Don't create value aliases when legalizing ABI boundaries.
When converting from ABI types to original program types, the final
conversion instruction can place its result into the original value, so
it doesn't need to be changed to an alias.
2017-04-13 10:16:58 -07:00
Jakob Stoklund Olesen
d48f79aa72 Avoid creating aliases when expanding legalizer patterns.
Now that we can detach and reuse all values, there is no longer a need
to create a lot of alias values during pattern expansion. Instead, reuse
the values from the source pattern when emitting instructions in the
destination pattern.

If a destination instruction produces the exact same values as a source
instruction, simply leave the values attached and replace the
instruction it. Otherwise, detach the source values, reuse them in the
expansion, and remove the source instruction afterwards.
2017-04-13 09:30:21 -07:00
Jakob Stoklund Olesen
18b567f88e Flatten the Value reference representation.
All values are now references into the value table, so drop the
distinction between direct and table values. Direct values don't exist
any more.

Also remove the parser support for the 'vxNN' syntax. Only 'vNN' values
can be parsed now.
2017-04-12 14:45:22 -07:00
Jakob Stoklund Olesen
8a2398be08 Stop calling Value::new_direct.
We only ever create table values now.

Simplify legalizer::legalize_inst_results. Instead of calling
detach_secondary_results, just detach all the results and don't treat
the first result specially.
2017-04-12 14:32:13 -07:00
Jakob Stoklund Olesen
94e26a845a Make tests less sensitive to specific value numbers. 2017-04-12 14:32:13 -07:00
Jakob Stoklund Olesen
4ee519e620 Add RISC-V call instruction encodings.
Calls are jal with a fixed %x1 link register.
2017-04-11 10:40:38 -07:00
Jakob Stoklund Olesen
aad6ebebb5 Add load and store instructions.
Define a MemFlags class, currently holding a notrap and aligned flag.
2017-04-11 09:54:55 -07:00
Jakob Stoklund Olesen
b474485c0d Add heap_load, heap_store, and heap_addr instructions.
These are used when lowering WebAssembly sandbox code.
2017-04-10 15:04:33 -07:00
Jakob Stoklund Olesen
222ae8af22 Define stack_load, stack_store, and stack_addr instructions. 2017-04-10 13:56:57 -07:00
Jakob Stoklund Olesen
51dea9f784 Syntax tweak: Omit comma after an initial enum immediate.
This affects the comparison instructions which now read "icmp ult a, b".
This mimics LLVM's style and makes it simpler to add instruction flags
in the future, such as "load v1" -> "load aligned v1".

These enumerated operands and flags feel like opcode modifiers rather
than value operands, so displaying them differently makes sense.

Value and numeric operands are still comma separated.
2017-04-10 10:28:37 -07:00
Jakob Stoklund Olesen
896ac935b9 Add jump encodings to RISC-V.
Fix a bug in gen_encoding.py when dealing with non-polymorphic
instructions where the type variable is None in Python, VOID in Rust.
2017-04-06 15:17:57 -07:00
Jakob Stoklund Olesen
fa4f151b9b Add a fallthrough instruction.
Change jumps to fallthroughs in the branch relaxation pass before
computing the EBB offsets.
2017-04-06 14:22:32 -07:00
Jakob Stoklund Olesen
856a67ca3a Use EBB offsets for encoding RISC-V branches.
Stop emitting EBB relocations. Use the offsets computed by
relax_branches() to encode the correct displacements immediately.
2017-04-06 12:55:57 -07:00
Jakob Stoklund Olesen
8a3f538441 Fix a bug in the binemit file test.
Only emit each instruction once, or the offset computations go all
wrong.
2017-04-06 11:17:46 -07:00
Jakob Stoklund Olesen
e641c97670 Add RISC-V encodings for brz and brnz.
These branches compare a register to zero. RISC-V implements this with
the %x0 hard-coded zero register.
2017-04-03 15:20:57 -07:00
Jakob Stoklund Olesen
479ff156c1 Add conditional branch encodings for RISC-V.
Not all br_icmp opcodes are present in the ISA. The missing ones can be
reached by commuting operands.

Don't attempt to encode EBB offsets yet. For now just emit an EBB
relocation for the branch instruction.
2017-04-03 15:16:25 -07:00
Jakob Stoklund Olesen
1b6a6f4e48 Add the br_icmp instruction.
This instruction behaves like icmp fused with brnz, and it can be used
to represent fused compare+branch instruction on Intel when optimizing
for macro-op fusion.

RISC-V provides compare-and-branch instructions directly, and it is
needed there too.
2017-04-03 15:04:42 -07:00
Jakob Stoklund Olesen
0530e822d4 Add RISC-V encodings for lui.
This instruction can materialize constants with the low 12 bits clear.
2017-04-03 12:27:22 -07:00
Jakob Stoklund Olesen
4e398164d2 Add icmp_imm encodings for RISC-V.
The ISA has icmp_imm slt/ult with 12-bit signed immediate operands.
2017-04-03 10:59:28 -07:00
Jakob Stoklund Olesen
e23d12bbc7 Add an icmp_imm instruction.
Compare a scalar integer to an immediate constant. Both Intel and RISC-V
ISAs have this operation.

This requires the addition of a new IntCompareImm instruction format.
2017-04-03 09:49:44 -07:00
Jakob Stoklund Olesen
9ddbc5d861 Emit Rshamt-type instructions for RISC-V.
These are the shift-by-immediate instructions.
2017-03-31 15:33:21 -07:00
Jakob Stoklund Olesen
c9a14448b8 Emit I-type instructions for RISC-V.
These are the BinaryImm formats.
2017-03-31 15:15:20 -07:00
Jakob Stoklund Olesen
e9907fbdd6 Add RISC-V encodings for supported icmp variants.
Only slt and ult variants are in the instruction set. Other condition
codes must be synthesized.
2017-03-31 13:47:07 -07:00
Jakob Stoklund Olesen
b5d4046591 Fix a type error in the legalizer patterns.
The carry and borrow values are boolean, so we have to convert them to
an integer type with bint(c) before we can add them to the result.

Also tweak the default legalizer action for unsupported types: Only
attempt a narrowing pattern for lane types > 32 bits.

This was found by @angusholder's new type checks in the verifier.
2017-03-29 15:00:27 -07:00
Jakob Stoklund Olesen
4613cbcf18 Test binary encodings of some RV32I instructions.
These are the R-format instructions in RV32I.
2017-03-29 13:16:12 -07:00
Jakob Stoklund Olesen
6ad34f90aa Allow for unencoded instructions in the binemit tests.
If an instruction doesn't have an associated encoding, use the standard
TargetIsa hook to encode it.

The test still fails if an instruction can't be encoded. There is no
legalization step.
2017-03-29 09:55:49 -07:00
Jakob Stoklund Olesen
f540cb0664 Add a binemit test command.
This makes it possible to write file tests that verify the binary
encoding of machine code.
2017-03-28 15:56:30 -07:00
Jakob Stoklund Olesen
d9f325f6cd Simplify branch arguments after splitting EBB arguments.
The EBB argument splitting may generate concat-split dependencies when
it repairs branch arguments in EBBs that have not yet been fully
legalized. Add a branch argument simplification step that can resolve
these dependency chains.

This means that all split and concatenation instructions will be dead
after legalization for types that have no legal instructions using them.
2017-03-22 15:29:06 -07:00
Keith Yeung
c7e25e6a35 Limit type inference for controlling type variables in write.rs 2017-03-22 14:45:38 -07:00
Jakob Stoklund Olesen
272df6489c Iteratively split EBB arguments.
When the legalizer splits a value into halves, it would previously stop
if the value was an EBB argument. With this change, we also split EBB
arguments and iteratively split arguments on branches to the EBB.

The iterative splitting stops when we hit the entry block arguments or
an instruction that isn't one of the concatenation instructions.
2017-03-22 13:12:19 -07:00
Jakob Stoklund Olesen
697246658d Avoid generating value split instructions.
The legalizer often splits values into parts with the vsplit and
isplit_lohi instructions. Avoid doing that for values that are already
defined by the corresponding concatenation instructions.

This reduces the number of instructions created during legalization, and
it simplifies later optimizations. A number of dead concatenation
instructions are left behind. They can be trivially cleaned up by a dead
code elimination pass.
2017-03-21 15:10:50 -07:00
Jakob Stoklund Olesen
2a321f42fb Strip the _lohi suffix from the isplit instructions.
For symmetry with the vector splitting instructions, we now have:

    isplit iconcat
    vsplit vconcat

No functional change.
2017-03-21 13:22:50 -07:00
Jakob Stoklund Olesen
f15651132b Fix a bug in analyze_call().
The call arguments on call_indirect should not include the fixed callee
argument.

Add legalizer assertions to verify that signatures are actually valid
after legalization. If not, we would get infinite legalizer loops.
2017-03-17 12:34:03 -07:00
Jakob Stoklund Olesen
d881ed331b Legalize return values from call instructions.
Like the entry block arguments, the return values from a call
instruction need to be converted back from their ABI representation.

Add tests of call instruction legalization.
2017-03-17 11:03:32 -07:00
Jakob Stoklund Olesen
4964502782 Break out differently purposed tests from abi.cton.
- abi.cton is for testing the actual RISC-V ABI.
- legalize-abi.cton is for testing the legalizer around ABI boundaries.
- parse-encoding.cton is for testing the parser's handling of RISC-V
  encoding and register annotations.
2017-03-17 10:07:32 -07:00