Commit Graph

2565 Commits

Author SHA1 Message Date
Alex Crichton
9e87e45745 Update wasmparser, wast, and spec test suite (#2264)
This brings in a number of SIMD opcode renames, various other test suite
updates, as well as some new proposed SIMD opcodes too.
2020-10-05 13:51:16 -05:00
Alex Crichton
2c6841041d Validate modules while translating (#2059)
* Validate modules while translating

This commit is a change to cranelift-wasm to validate each function body
as it is translated. Additionally top-level module translation functions
will perform module validation. This commit builds on changes in
wasmparser to perform module validation interwtwined with parsing and
translation. This will be necessary for future wasm features such as
module linking where the type behind a function index, for example, can
be far away in another module. Additionally this also brings a nice
benefit where parsing the binary only happens once (instead of having an
up-front serial validation step) and validation can happen in parallel
for each function.

Most of the changes in this commit are plumbing to make sure everything
lines up right. The major functional change here is that module
compilation should be faster by validating in parallel (or skipping
function validation entirely in the case of a cache hit). Otherwise from
a user-facing perspective nothing should be that different.

This commit does mean that cranelift's translation now inherently
validates the input wasm module. This means that the Spidermonkey
integration of cranelift-wasm will also be validating the function as
it's being translated with cranelift. The associated PR for wasmparser
(bytecodealliance/wasmparser#62) provides the necessary tools to create
a `FuncValidator` for Gecko, but this is something I'll want careful
review for before landing!

* Read function operators until EOF

This way we can let the validator take care of any issues with
mismatched `end` instructions and/or trailing operators/bytes.
2020-10-05 11:02:01 -05:00
Benjamin Bouvier
df8f85f4bc machinst x64: remove non_camel_case_types; 2020-10-05 17:44:31 +02:00
Benjamin Bouvier
4a10a78e33 machinst x64: remove non_snake_case; 2020-10-05 17:44:31 +02:00
Johnnie Birch
5799fd3cc0 Add file test simd-arithmetic-run to x64 backend
Copies over simd-arithmetic-run from the old backend, adding
several run tests including for min/max. Tests not supported
are commented out.
2020-10-02 16:20:10 -07:00
Johnnie Birch
7b4d173b90 Adds packed floating point min/max for X64 for the new backend
Allows for simd_f32x4 and simd_f64x2 spec tests
2020-10-02 16:20:10 -07:00
Chris Fallin
3ca173e4bc Fix arm32 build after some ABI framework changes.
It turns out that while we don't have the partial/experimental arm32
backend tested on our CI yet, the Firefox build *does* at least rely on
the backend to build, because it specifies the `arm32` feature to
`cranelift-codegen`, even if it will never invoke the backend.
Our previous old-framework arm32 stub at least compiled, so it didn't
break Firefox.

We should probably add a CI build check to ensure we don't bitrot what
we have here, but this is the immediate fix to get us back to sanity.
2020-10-02 11:55:46 -07:00
Chris Fallin
b2f52910fb Merge pull request #2224 from jgouly/sp_adjust
arm64: Use SignedOffset rather than PreIndexed addressing mode for ca…
2020-10-02 09:18:00 -07:00
Andrew Brown
ca1b76421a [machinst x64]: remove duplicate code to insert a lane 2020-10-02 08:29:31 -07:00
Andrew Brown
c42a097a0c [machinst x64]: use is64 instead of w_bit 2020-10-02 08:29:31 -07:00
Andrew Brown
16a2538ecd [machinst x64]: rename Inst::XmmUninitializedValue and document
This approach is not the best but avoids an extra instruction; perhaps at some point, as mentioned in https://github.com/bytecodealliance/wasmtime/pull/2248, we will add the extra instruction or refactor things in such a way that this `Inst` variant is unnecessary.
2020-10-02 08:29:31 -07:00
Andrew Brown
3d9f3bf728 [machinst x64]: port CLIF tests related to comparison and lane operations 2020-10-02 08:29:31 -07:00
Andrew Brown
50b9399006 [machinst x64]: lower remaining lane operations--any_true, all_true, splat 2020-10-02 08:29:31 -07:00
Andrew Brown
4565582f02 [machinst x64]: clarify parameter name of Inst::xmm_rm_r_imm 2020-10-02 08:29:31 -07:00
Andrew Brown
0579e9f9de [machinst x64]: add packed OR 2020-10-02 08:29:31 -07:00
Andrew Brown
74226d6781 [machinst x64]: add integer comparisons 2020-10-02 08:29:31 -07:00
Joey Gouly
eec60c9b06 arm64: Use SignedOffset rather than PreIndexed addressing mode for callee-saved registers
This also passes `fixed_frame_storage_size` (previously `total_sp_adjust`)
into `gen_clobber_save` so that it can be combined with other stack
adjustments.

Copyright (c) 2020, Arm Limited.
2020-10-02 16:22:55 +01:00
Chris Fallin
5c1d728e3a Merge pull request #2228 from akirilov-arm/vector_callee_saves
AArch64: Add test cases for callee-saved SIMD & FP registers
2020-10-01 17:08:33 -07:00
Chris Fallin
b8f0dc429f Merge pull request #2223 from cfallin/baldrdash-2020
Support for SpiderMonkey's "Wasm ABI 2020" in general and on AArch64.
2020-09-30 15:33:05 -07:00
Chris Fallin
835db11bea Support for SpiderMonkey's "Wasm ABI 2020".
As part of a Wasm JIT update, SpiderMonkey is changing its internal
WebAssembly function ABI. The new ABI's frame format includes "caller
TLS" and "callee TLS" slots. The details of where these come from are
not important; from Cranelift's point of view, the only relevant
requirement is that we have two on-stack args that are always present
(offsetting other on-stack args), and that we define special argument
purposes so that we can supply values for these slots.

Note that this adds a *new* ABI (a variant of the Baldrdash ABI) because
we do not want to tightly couple the landing of this PR to the landing
of the changes in SpiderMonkey; it's better if both the old and new
behavior remain available in Cranelift, so SpiderMonkey can continue to
vendor Cranelift even if it does not land (or backs out) the ABI change.

Furthermore, note that this needs to be a Cranelift-level change (i.e.
cannot be done purely from the translator environment implementation)
because the special TLS arguments must always go on the stack, which
would not otherwise happen with the usual argument-placement logic; and
there is no primitive to push a value directly in CLIF code (the notion
of a stack frame is a lower-level concept).
2020-09-30 14:55:56 -07:00
Anton Kirilov
d18de69e5a AArch64: Add test cases for callee-saved SIMD & FP registers
Copyright (c) 2020, Arm Limited.
2020-09-30 14:19:02 +01:00
Alex Crichton
a04001211c Add metadata to peepmatic crates (#2245) 2020-09-29 18:56:08 -05:00
Andrew Brown
4484a00ea5 [machinst x64]: calculate extension modes in one place 2020-09-29 14:48:59 -07:00
Andrew Brown
715be68101 [machinst x64]: assert lane is correct size for extractlane
This change applies a good suggestion @bjorn3 made in #2230 that I forgot to implement there.
2020-09-29 09:34:22 -07:00
Andrew Brown
b43f4a464a refactor: move all 'filetests/vcode' tests to 'filetests/isa' 2020-09-29 09:27:39 -07:00
Andrew Brown
452d854855 [machinst x64]: demonstrate that packed register moves are elided 2020-09-29 08:48:37 -07:00
Andrew Brown
b7217d454f [machinst x64]: add lane-related CLIF filetests 2020-09-29 08:45:12 -07:00
Andrew Brown
f50d905152 [machinst x64]: refactor using added RegMem::from(Writable<Reg>) 2020-09-29 08:45:12 -07:00
Andrew Brown
e3eb098c99 [machinst x64]: add swizzle implementation 2020-09-29 08:45:12 -07:00
Andrew Brown
050f078f86 [machinst x64]: add saturating addition implementation 2020-09-29 08:45:12 -07:00
Andrew Brown
a64abf9b76 [machinst x64]: add shuffle implementation 2020-09-29 08:45:12 -07:00
Andrew Brown
f4836f9ca9 [machinst x64]: add extractlane implementation 2020-09-29 08:45:12 -07:00
Andrew Brown
29fa894790 [machinst x64]: add insertlane implementation 2020-09-29 08:45:12 -07:00
Pat Hickey
b10beeee01 dep gardening (#2233)
* wasmtime-profiling: latest object dep is 0.21.1

* latest gimli is 0.22

* bump cargo.lock
2020-09-26 00:49:28 -05:00
Andrew Brown
48cf45491d [machinst x64]: inform the register allocator of more types of packed moves 2020-09-25 18:59:01 -07:00
Benjamin Bouvier
e2c286deeb machinst x64: enable clif testing
This adds a new feature experimental_x64 for CLIF tests.

A test is run in the new x64 backend iff:

- either the test doesn't have an x86_64 target requirement, signaling
it must be target agnostic or not run on this target.
- or the test does require the x86_64 target, and the test is marked
with the `experimental_x64` feature.

This required one workaround in the parser. The reason is that the
parser will try to use information not provided by the TargetIsa adapter
for the Mach backends, like register names. In particular, parsing test
may fail before the test runner realizes that the test must not be run.
In this case, we early return an almost-empty TestFile from the parser,
under the same conditions as above, so that the caller may filter out
the test properly.

This also copies two tests from the test suite using the new backend,
for demonstration purposes.
2020-09-25 11:12:21 +02:00
Andrew Brown
ac2bf9d246 [machinst x64]: add packed min/max implementations 2020-09-23 15:40:46 -07:00
Andrew Brown
7546d98844 [machinst x64]: add avg_round implementation 2020-09-23 15:40:46 -07:00
Andrew Brown
b202464fa0 [machinst x64]: add iabs implementation 2020-09-23 15:40:46 -07:00
Alex Crichton
5e08eb3b83 Bump wasmtime to 0.20.0 (#2222)
At the same time bump cranelift crates to 0.67.0
2020-09-23 13:54:02 -05:00
Nikolay Volf
0ec2c12ab5 Log level to "debug!" in translate_from_reader (#2221)
Default logger floods the console otherwise:

```
Sep 22 22:41:02.525 INFO translate(181 bytes, u0:1353(i64 vmctx, i64, i32, i32) -> i32 system_v)
Sep 22 22:41:02.526 INFO translate(394 bytes, u0:1354(i64 vmctx, i64, i32) system_v)
Sep 22 22:41:02.527 INFO translate(16307 bytes, u0:944(i64 vmctx, i64, i32, i32, i32) system_v)
Sep 22 22:41:02.528 INFO translate(269 bytes, u0:382(i64 vmctx, i64, i32, i32) system_v)
Sep 22 22:41:02.528 INFO translate(220 bytes, u0:283(i64 vmctx, i64, i32, i32) system_v)
Sep 22 22:41:02.528 INFO translate(603 bytes, u0:383(i64 vmctx, i64, i32, i32) system_v)
Sep 22 22:41:02.528 INFO translate(1470 bytes, u0:284(i64 vmctx, i64, i32, i32) system_v)
Sep 22 22:41:02.529 INFO translate(189 bytes, u0:387(i64 vmctx, i64, i32, i32) -> i32 system_v)
Sep 22 22:41:02.529 INFO translate(14 bytes, u0:388(i64 vmctx, i64, i32, i32) system_v)
```
2020-09-23 17:06:53 +02:00
Benjamin Bouvier
79cff73da5 machinst x64: implement loads/stores for v128 SIMD types;
This made it possible to enable more SIMD tests from the spec test suite
too.
2020-09-23 16:42:03 +02:00
Pat Hickey
1fabb051b0 Merge pull request #2218 from bjorn3/per_function_sections
cranelift-object: Support per function sections
2020-09-22 11:28:58 -07:00
Pat Hickey
2308502336 Merge pull request #2212 from bjorn3/fix_custom_section_rel_ro
Fix relocated readonly data in custom sections
2020-09-22 11:28:32 -07:00
bjorn3
863d4272a7 cranelift-object: Support per function sections
This makes it possible for the linker to omit unused functions when
--gc-sections is passed.
2020-09-22 14:04:15 +02:00
Jakub Krauz
bab3c73100 Put arm32 backend behind experimental_arm32 flag 2020-09-22 12:53:14 +02:00
Jakub Krauz
f6a140a662 arm32 codegen
This commit adds arm32 code generation for some IR insts.
Floating-point instructions are not supported, because regalloc
does not allow to represent overlapping register classes,
which are needed by VFP/Neon.

There is also no support for big-endianness, I64 and I128 types.
2020-09-22 12:49:42 +02:00
bjorn3
45ccc6940e Fix Switch for 128bit integers 2020-09-21 14:50:59 +02:00
bjorn3
deb20c129a Fix relocated readonly data in custom sections
Lld doesn't allow relocations in readonly sections
2020-09-21 13:38:42 +02:00
Nick Fitzgerald
010e5b9aa8 Make filetest errors report full context (#2207)
* clif-util: do not convert `anyhow::Error`s into strings into `anyhow::Error`s

* filetests: Use the debug formatting of `anyhow::Error`s

This provides the full error context, not just the source error's message.
2020-09-18 13:33:38 -05:00