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e15c332471f6a977410f7e8656b9b9b337ccf2ed
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17 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
e15c332471 Encode iconst.i32 for RISC-V. 
For large constants with the low 12 bits clear, we already have the
"lui" encoding. Add "addi %x0" encodings for signed 12-bit constants.
 2017-06-22 12:13:37 -07:00
Jakob Stoklund Olesen
4503306f0e Add RISC-V encodings for call_indirect. 2017-06-14 16:14:16 -07:00
Jakob Stoklund Olesen
3e1e2b6e5e Add RISC-V encodings for copy instructions. 2017-06-14 15:36:25 -07:00
Jakob Stoklund Olesen
5336bbd4cc Add RISC-V encodings for spill and fill. 
Add a Stack() class for specifying operand constraints for values on the
stack.

Add encoding recipes for RISC-V spill and fill instructions. Don't
implement the encoding recipe functions yet since we don't have the
stack slot layout yet.
 2017-06-13 13:39:52 -07:00
Jakob Stoklund Olesen
d66a9d196e Implement binary emission of RISC-V return instructions. 
The return address is now always supplied in %x1, so the return address
predictor will recognize the jalr as a return and not some indirect
branch.
 2017-04-19 16:26:04 -07:00
Jakob Stoklund Olesen
4ee519e620 Add RISC-V call instruction encodings. 
Calls are jal with a fixed %x1 link register.
 2017-04-11 10:40:38 -07:00
Jakob Stoklund Olesen
896ac935b9 Add jump encodings to RISC-V. 
Fix a bug in gen_encoding.py when dealing with non-polymorphic
instructions where the type variable is None in Python, VOID in Rust.
 2017-04-06 15:17:57 -07:00
Jakob Stoklund Olesen
856a67ca3a Use EBB offsets for encoding RISC-V branches. 
Stop emitting EBB relocations. Use the offsets computed by
relax_branches() to encode the correct displacements immediately.
 2017-04-06 12:55:57 -07:00
Jakob Stoklund Olesen
1984c96f7c rustfmt 0.8.1 2017-04-05 09:00:11 -07:00
Jakob Stoklund Olesen
e641c97670 Add RISC-V encodings for brz and brnz. 
These branches compare a register to zero. RISC-V implements this with
the %x0 hard-coded zero register.
 2017-04-03 15:20:57 -07:00
Jakob Stoklund Olesen
479ff156c1 Add conditional branch encodings for RISC-V. 
Not all br_icmp opcodes are present in the ISA. The missing ones can be
reached by commuting operands.

Don't attempt to encode EBB offsets yet. For now just emit an EBB
relocation for the branch instruction.
 2017-04-03 15:16:25 -07:00
Jakob Stoklund Olesen
0530e822d4 Add RISC-V encodings for lui. 
This instruction can materialize constants with the low 12 bits clear.
 2017-04-03 12:27:22 -07:00
Jakob Stoklund Olesen
4e398164d2 Add icmp_imm encodings for RISC-V. 
The ISA has icmp_imm slt/ult with 12-bit signed immediate operands.
 2017-04-03 10:59:28 -07:00
Jakob Stoklund Olesen
9ddbc5d861 Emit Rshamt-type instructions for RISC-V. 
These are the shift-by-immediate instructions.
 2017-03-31 15:33:21 -07:00
Jakob Stoklund Olesen
c9a14448b8 Emit I-type instructions for RISC-V. 
These are the BinaryImm formats.
 2017-03-31 15:15:20 -07:00
Jakob Stoklund Olesen
e9907fbdd6 Add RISC-V encodings for supported icmp variants. 
Only slt and ult variants are in the instruction set. Other condition
codes must be synthesized.
 2017-03-31 13:47:07 -07:00
Jakob Stoklund Olesen
0619d6f827 Generate binemit::emit_inst() functions. 
Use the meta language encoding recipes to generate an emit_inst()
function for each ISA. The generated calls into recipe_*() functions
that must be implemented by hand.

Implement recipe_*() functions for the RISC-V recipes.

Add the TargetIsa::emit_inst() entry point which emits an instruction to
a CodeSink trait object.
 2017-03-28 14:44:36 -07:00