Commit Graph

958 Commits

Author SHA1 Message Date
Damian Heaton
dd23a21b9b Implement Swizzle and Splat for interpreter (#3268)
* Implement `Swizzle` and `Splat` for interpreter

Implemented for the Cranelift interpreter:
- `Swizzle` to shuffle an `i8x16` SIMD vector based
on the indices specified in another vector of the same size.
- `Splat` to create a SIMD vector with all lanes having the same value.

Copyright (c) 2021, Arm Limited

* Fix old x86 backend failing test

Copyright (c) 2021, Arm Limited

* Represent i16x8 and above as hex

Copyright (c) 2021, Arm Limited
2021-09-07 09:53:49 -07:00
Afonso Bordado
63e9a81deb Implement vany_true and vall_true instructions in interpreter (#3304)
* cranelift: Implement ZeroExtend for a bunch of types in interpreter

* cranelift: Implement VConst on interpreter

* cranelift: Implement VallTrue on interpreter

* cranelift: Implement VanyTrue on interpreter

* cranelift: Mark `v{all,any}_true` tests as machinst only

* cranelift: Disable `vany_true` tests on aarch64

The `b64x2` case produces an illegal instruction. See #3305
2021-09-07 09:50:39 -07:00
Chris Fallin
ecd795f736 Merge pull request #3290 from dheaton-arm/implement-ssatarith
Implement `SaddSat` and `SsubSat` for the Cranelift interpreter
2021-09-03 09:48:34 -07:00
Chris Fallin
e3ccff0249 Merge pull request #3283 from dheaton-arm/implement-umulhi
Implement `Umulhi` for the interpreter
2021-09-03 09:29:21 -07:00
dheaton-arm
8f057e0482 Implement SaddSat and SsubSat for the interpreter
Implemented `SaddSat` and `SsubSat` to add and subtract signed vector
values, saturating at the type boundaries rather than overflowing.

Changed the parser to allow signed `i8` immediates in vectors as part of
this work; fixes #3276.

Copyright (c) 2021, Arm Limited.
2021-09-03 11:35:39 +01:00
dheaton-arm
562947c678 Fix CI tests + rename tests
- Fixed CI tests for AArch64 and old x86.
- Rename `simd-umulhi.clif` to `umulhi.clif`.
- Rename `simd-umulhi-aarch64.clif` to `simd-umulhi.clif`.

Copyright (c) 2021, Arm Limited.
2021-09-03 10:37:24 +01:00
Chris Fallin
d6a77898ba Merge pull request #3272 from dheaton-arm/implement-iaddpairwise
Implement `IaddPairwise` for the interpreter
2021-09-02 10:52:47 -07:00
Chris Fallin
6e05b646a3 Merge pull request #3282 from afonso360/x64-fix-brtables
cranelift: Fix `br_table` for `i64` types in x64 backend.
2021-09-02 09:58:42 -07:00
Chris Fallin
000a97f4ff Merge pull request #3279 from dheaton-arm/implement-insertlane
Implement `Insertlane` for the Cranelift interpreter
2021-09-02 09:44:59 -07:00
Afonso Bordado
f9ada24bcf cranelift: Fix br_table for i64 inputs
We still only support a maximum of u32::MAX entries, however we no
longer crash when compiling 64 bit indexes.

Fixes #3100
2021-09-02 15:31:48 +01:00
dheaton-arm
16b6a404e4 Implement Umulhi for the interpreter
Implemented `Umulhi` for the Cranelift interpreter, performing unsigned
integer multiplication and producing the high half of a double-length
result.

Fixed `ExtractUpper` conversion behaviour as part of this change, which
was extracting from a 128-bit value regardless of the size of the
original value.

Copyright (c) 2021, Arm Limited.
2021-09-02 13:11:41 +01:00
Chris Fallin
91410aaddf Merge pull request #3234 from dheaton-arm/implement-isubb
Implement `IsubBin`, `IsubBout`, and `IsubBorrow`for Cranelift interpreter
2021-09-01 11:25:43 -07:00
dheaton-arm
d956d349d8 Implement Insertlane for the Cranelift interpreter
Implemented `Insertlane` to insert a value in the lane specified by the
immediate value, overwriting the existing value in that lane.

Added `TernaryImm8` support for the `imm_value` function.

Copyright (c) 2021, Arm Limited.
2021-09-01 16:21:27 +01:00
Afonso Bordado
f9f5ae59a6 cranelift: Merge interpreter tests with runtests (#3252)
Almost all the tests in the interpreter are already in the runtests
folder so that we can reuse them for the backends. The distinction
between interpreter tests and runtests is no longer very clear, since
they should both support the same clif code, and produce the same results.

We only have two test files:

* `add.clif` tests the add and jump instruction, both of which are
already covered in other test files, so we remove that file.

* `fibonacci.clif` does a recursive call which is currently not supported
in the filetest environment, so we keep this test interpreter only for now.
2021-09-01 06:42:02 -07:00
dheaton-arm
7a5646c5f4 Implement IaddPairwise for the interpreter
Implemented `IaddPairwise` for the Cranelift interpreter, to add pairs
of adjacent values in two SIMD vectors, concatenating them at the end
(preserving both lane size and number of lanes).

Copyright (c) 2021, Arm Limited
2021-09-01 13:53:26 +01:00
Damian Heaton
4378ea8e01 Implement IaddCin, IaddCout, and IaddCarry for Cranelift interpreter (#3233)
* Implement `IaddCin`, `IaddCout`, and `IaddCarry` for Cranelift interpreter

Implemented the following Opcodes for the Cranelift interpreter:
- `IaddCin` to add two scalar integers with an input carry flag.
- `IaddCout` to add two scalar integers and report overflow with the carry flag.
- `IaddCarry` to add two scalar integers with an input carry flag, reporting overflow with the output carry flag.

Copyright (c) 2021, Arm Limited

* Simplify carry check + add i64 `IaddCarry` tests

Copyright (c) 2021, Arm Limited

* Move tests to `runtests`

Copyright (c) 2021, Arm Limited
2021-08-31 09:29:38 -07:00
dheaton-arm
d1fe72affa Add i64 tests to IsubBorrow and move tests.
Copyright (c) 2021, Arm Limited
2021-08-31 11:47:26 +01:00
bjorn3
b79e59882d Fix tests 2021-08-27 18:28:33 +02:00
bjorn3
8adb40b2b8 Add tests 2021-08-27 17:48:04 +02:00
Anton Kirilov
7b98be1bee Cranelift: Simplify leaf functions that do not use the stack (#2960)
* Cranelift AArch64: Simplify leaf functions that do not use the stack

Leaf functions that do not use the stack (e.g. do not clobber any
callee-saved registers) do not need a frame record.

Copyright (c) 2021, Arm Limited.
2021-08-27 12:12:37 +02:00
Damian Heaton
02ef6a02b8 Implement Extractlane, UaddSat, and UsubSat for Cranelift interpreter (#3188)
* Implement `Extractlane`, `UaddSat`, and `UsubSat` for Cranelift interpreter

Implemented the `Extractlane`, `UaddSat`, and `UsubSat` opcodes for the interpreter,
and added helper functions for working with SIMD vectors (`extractlanes`, `vectorizelanes`,
and `binary_arith`).

Copyright (c) 2021, Arm Limited

* Re-use tests + constrict Vector assert

- Re-use interpreter tests as runtests where supported.
- Constrict Vector assertion.
- Code style adjustments following feedback.

Copyright (c) 2021, Arm Limited

* Runtest `i32x4` vectors on AArch64; add `i64x2` tests

Copyright (c) 2021, Arm Limited

* Add `simd-` prefix to test filenames

Copyright (c) 2021, Arm Limited

* Return aliased `SmallVec` from `extractlanes`

Using a `SmallVec<[i128; 4]>` allows larger-width 128-bit vectors
(`i32x4`, `i64x2`, ...) to not cause heap allocations.

Copyright (c) 2021, Arm Limited

* Accept slice to `vectorizelanes` rather than `Vec`

Copyright (c) 2021, Arm Limited
2021-08-25 09:03:19 -07:00
Afonso Bordado
2776074dfc cranelift: Add stack support to the interpreter with virtual addresses (#3187)
* cranelift: Add stack support to the interpreter

We also change the approach for heap loads and stores.

Previously we would use the offset as the address to the heap. However,
this approach does not allow using the load/store instructions to
read/write from both the heap and the stack.

This commit changes the addressing mechanism of the interpreter. We now
return the real addresses from the addressing instructions
(stack_addr/heap_addr), and instead check if the address passed into
the load/store instructions points to an area in the heap or the stack.

* cranelift: Add virtual addresses to cranelift interpreter

Adds a  Virtual Addressing scheme that was discussed as a better
alternative to returning the real addresses.

The virtual addresses are split into 4 regions (stack, heap, tables and
global values), and the address itself is composed of an `entry` field
and an `offset` field. In general the `entry` field corresponds to the
instance of the resource (e.g. table5 is entry 5) and the `offset` field
is a byte offset inside that entry.

There is one exception to this which is the stack, where due to only
having one stack, the whole address is an offset field.

The number of bits in entry vs offset fields is variable with respect to
the `region` and the address size (32bits vs 64bits). This is done
because with 32 bit addresses we would have to compromise on heap size,
or have a small number of global values / tables. With 64 bit addresses
we do not have to compromise on this, but we need to support 32 bit
addresses.

* cranelift: Remove interpreter trap codes

* cranelift: Calculate frame_offset when entering or exiting a frame

* cranelift: Add safe read/write interface to DataValue

* cranelift: DataValue write full 128bit slot for booleans

* cranelift: Use DataValue accessors for trampoline.
2021-08-24 09:29:11 -07:00
Afonso Bordado
f4ff7c350a cranelift: Add heap support to filetest infrastructure (#3154)
* cranelift: Add heap support to filetest infrastructure

* cranelift: Explicit heap pointer placement in filetest annotations

* cranelift: Add documentation about the Heap directive

* cranelift: Clarify that heap filetests pointers must be laid out sequentially

* cranelift: Use wrapping add when computing bound pointer

* cranelift: Better error messages when invalid signatures are found for heap file tests.
2021-08-24 09:28:41 -07:00
Afonso Bordado
3f6b889067 cranelift: Prevent panics when dividing INT_MIN / -1 in interpreter 2021-08-24 09:27:54 -07:00
dheaton-arm
721cfc16b3 Implement IsubBin, IsubBout, and IsubBorrow
Implemented the following Opcodes for the Cranelift interpreter:
- `IsubBin` to subtract two scalar integers with an input borrow flag.
- `IsubBout` to subtract two scalar integers with an output borrow flag.
- `IsubBorrow` to subtract two scalar integers with an input and output borrow flag.

Copyright (c) 2021, Arm Limited
2021-08-24 09:38:17 +01:00
Anton Kirilov
a1b39276e1 Enable more CLIF tests on AArch64
The tests for the SIMD floating-point maximum and minimum operations
require particular care because the handling of the NaN values is
non-deterministic and may vary between platforms. There is no way to
match several NaN values in a test, so the solution is to extract the
non-deterministic test cases into a separate file that is subsequently
replicated for every backend under test, with adjustments made to the
expected results.

Copyright (c) 2021, Arm Limited.
2021-08-17 13:27:58 +01:00
Chris Fallin
7c0948fe0b Merge pull request #3102 from afonso360/fix-bool-trampolines
cranelift: Fix trampoline args for b1 types
2021-08-14 15:50:30 -07:00
Afonso Bordado
8862499529 cranelift: Fix trampoline args for b1 types
Our DataValues only have one size of booleans so we are always going to
have this mismatch of sizes
2021-08-08 17:42:50 +01:00
Sam Parker
b6f6ac116a Revert IR changes
Along with the x64 and s390x changes. Now pattern matching the
uextend(atomic_load) in the aarch64 backend.
2021-08-05 09:35:32 +01:00
Sam Parker
cbb7229457 Re-implement atomic load and stores
The AArch64 support was a bit broken and was using Armv7 style
barriers, which aren't required with Armv8 acquire-release
load/stores.

The fallback CAS loops and RMW, for AArch64, have also been updated
to use acquire-release, exclusive, instructions which, again, remove
the need for barriers. The CAS loop has also been further optimised
by using the extending form of the cmp instruction.

Copyright (c) 2021, Arm Limited.
2021-08-05 09:08:08 +01:00
Sam Parker
3bc2f0c701 Enable simd_X_extadd_pairwise_X for AArch64
Lower to [u|s]addlp for AArch64.

Copyright (c) 2021, Arm Limited.
2021-08-03 10:25:09 +01:00
Chris Fallin
a13a777230 Bump to Wasmtime v0.29.0 and Cranelift 0.76.0. 2021-08-02 11:24:09 -07:00
Alex Crichton
63a3bbbf5a Change VMMemoryDefinition::current_length to usize (#3134)
* Change VMMemoryDefinition::current_length to `usize`

This commit changes the definition of
`VMMemoryDefinition::current_length` to `usize` from its previous
definition of `u32`. This is a pretty impactful change because it also
changes the cranelift semantics of "dynamic" heaps where the bound
global value specifier must now match the pointer type for the platform
rather than the index type for the heap.

The motivation for this change is that the `current_length` field (or
bound for the heap) is intended to reflect the current size of the heap.
This is bound by `usize` on the host platform rather than `u32` or`
u64`. The previous choice of `u32` couldn't represent a 4GB memory
because we couldn't put a number representing 4GB into the
`current_length` field. By using `usize`, which reflects the host's
memory allocation, this should better reflect the size of the heap and
allows Wasmtime to support a full 4GB heap for a wasm program (instead
of 4GB minus one page).

This commit also updates the legalization of the `heap_addr` clif
instruction to appropriately cast the address to the platform's pointer
type, handling bounds checks along the way. The practical impact for
today's targets is that a `uextend` is happening sooner than it happened
before, but otherwise there is no intended impact of this change. In the
future when 64-bit memories are supported there will likely need to be
fancier logic which handles offsets a bit differently (especially in the
case of a 64-bit memory on a 32-bit host).

The clif `filetest` changes should show the differences in codegen, and
the Wasmtime changes are largely removing casts here and there.

Closes #3022

* Add tests for memory.size at maximum memory size

* Add a dfg helper method
2021-08-02 13:09:40 -05:00
Sam Parker
541a4ee428 Enable simd_extmul_* for AArch64
Lower simd_extmul_[low/high][signed/unsigned] to [s|u]widen inputs to
an imul node.

Copyright (c) 2021, Arm Limited.
2021-07-28 13:14:20 +01:00
Nick Fitzgerald
a2cfddff9c Merge pull request #3116 from fitzgen/update-gimli-and-addr2line
Update `gimli` to 0.25; `addr2line` to 0.16
2021-07-26 13:01:37 -07:00
Chris Fallin
0f068ac933 Merge pull request #3117 from fitzgen/log-levels
cranelift: Move most debug-level logs to the trace level
2021-07-26 12:52:39 -07:00
Nick Fitzgerald
4283d2116d cranelift: Move most debug-level logs to the trace level
Cranelift crates have historically been much more verbose with debug-level
logging than most other crates in the Rust ecosystem. We log things like how
many parameters a basic block has, the color of virtual registers during
regalloc, etc. Even for Cranelift hackers, these things are largely only useful
when hacking specifically on Cranelift and looking at a particular test case,
not even when using some Cranelift embedding (such as Wasmtime).

Most of the time, when people want logging for their Rust programs, they do
something like:

    RUST_LOG=debug cargo run

This means that they get all that mostly not useful debug logging out of
Cranelift. So they might want to disable logging for Cranelift, or change it to
a higher log level:

    RUST_LOG=debug,cranelift=info cargo run

The problem is that this is already more annoying to type that `RUST_LOG=debug`,
and that Cranelift isn't one single crate, so you actually have to play
whack-a-mole with naming all the Cranelift crates off the top of your head,
something more like this:

    RUST_LOG=debug,cranelift=info,cranelift_codegen=info,cranelift_wasm=info,...

Therefore, we're changing most of the `debug!` logs into `trace!` logs: anything
that is very Cranelift-internal, unlikely to be useful/meaningful to the
"average" Cranelift embedder, or prints a message for each instruction visited
during a pass. On the other hand, things that just report a one line statistic
for a whole pass, for example, are left as `debug!`. The more verbose the log
messages are, the higher the bar they must clear to be `debug!` rather than
`trace!`.
2021-07-26 11:50:16 -07:00
Nick Fitzgerald
3d76cbdf34 Update gimli to 0.25; addr2line to 0.16 2021-07-26 11:04:53 -07:00
Afonso Bordado
a2fb019ba7 cranelift: Add basic i128 support in interpreter 2021-07-23 11:22:07 -07:00
Afonso Bordado
6be4441bbf cranelift: Resolve alias lookups in interpreter 2021-07-22 10:42:29 -07:00
Afonso Bordado
065190f975 cranelift: Implement br_table on the interpreter 2021-07-20 15:31:27 -07:00
Afonso Bordado
04033fe645 cranelift: Implement overflow flags for icmp in interpreter 2021-07-19 09:31:14 -07:00
Afonso Bordado
c42b725ce9 cranelift: Fix br_icmp in interpreter 2021-07-19 09:31:14 -07:00
Afonso Bordado
004af01a88 cranelift: Fix brz,brnz instructions in the interpreter 2021-07-19 09:31:14 -07:00
Afonso Bordado
db5566dadb aarch64: Fix lowering amounts for shifts
This commit addresses two issues:
* A panic when shifting any non i128 type by i128 amounts (#3064)
* Wrong results when lowering shifts with small types (i8, i16)

In these types when shifting for amounts larger than the size of the
type, we would not get the wrapping behaviour that we see on i32 and i64.
This is because in these larger types, the wrapping behaviour is automatically
implemented by using the appropriate instruction, however we do not
have i8 and i16 specific instructions, so we have to manually wrap
the shift amount with an AND instruction.

This issue is also found on x86_64 and s390x, and a separate issue will
be filed for those.

Closes #3064
2021-07-16 22:08:02 +01:00
Afonso Bordado
eebae8d4c8 aarch64: Fix incorrect encoding of large const values in icmp.
When encoding constants as immediates into an RSE Imm12 instruction we need to take special care to check if the value that we are trying to input does not overflow its type when viewed as a signed value. (i.e. iconst.i8 200)

We cannot both put an immediate and sign extend it, so we need to lower it into a separate reg, and emit the sign extend into the instruction.

For more details see the [cg_clif bug report](https://github.com/bjorn3/rustc_codegen_cranelift/issues/1184#issuecomment-873214796).
2021-07-03 22:42:15 +01:00
Afonso Bordado
7453bd5f0d Cranelift CLIF-level differential fuzzer (#3038)
* cranelift: Initial fuzzer implementation

* cranelift: Generate multiple test cases in fuzzer

* cranelift: Separate function generator in fuzzer

* cranelift: Insert random instructions in fuzzer

* cranelift: Rename gen_testcase

* cranelift: Implement div for unsigned values in interpreter

* cranelift: Run all test cases in fuzzer

* cranelift: Comment options in function_runner

* cranelift: Improve fuzzgen README.md

* cranelift: Fuzzgen remove unused variable

* cranelift: Fuzzer code style fixes

Thanks! @bjorn3

* cranelift: Fix nits in CLIF fuzzer

Thanks @cfallin!

* cranelift: Implement Arbitrary for TestCase

* cranelift: Remove gen_testcase

* cranelift: Move fuzzers to wasmtime fuzz directory

* cranelift: CLIF-Fuzzer ignore tests that produce traps

* cranelift: CLIF-Fuzzer create new fuzz target to validate generated testcases

* cranelift: Store clif-fuzzer config in a separate struct

* cranelift: Generate variables upfront per function

* cranelift: Prevent publishing of fuzzgen crate
2021-07-01 06:32:01 -07:00
Afonso Bordado
a4770a7e28 cranelift: Prevent overflow errors in interpreter for add,sub,mul 2021-06-30 06:32:16 -07:00
Afonso Bordado
e85eb77c45 aarch64: Implement missing atomic rmw ops 2021-06-25 07:51:46 +01:00
Chris Fallin
652f21e3e0 Merge pull request #3026 from afonso360/aarch64-elf-tls
aarch64: Implement TLS ELF GD Relocations
2021-06-24 11:54:34 -07:00