Commit Graph

1892 Commits

Author SHA1 Message Date
Alex Crichton
5bd03d282f Update a number of wasmtime's dependencies (#1355)
* Run `cargo update`
* Use `cargo outdated` to guide some manual version bumps
2020-03-18 14:15:33 -05:00
Andrew Brown
057a0cf44e Organize SIMD arithmetic filetest; add REX-inducing register assignments 2020-03-18 10:12:50 -07:00
Andrew Brown
0d63bd12d8 Infer REX prefix for SIMD operations; fixes #1127
- Convert recipes to have necessary size calculator
- Add a missing binemit function, `put_dynrexmp3`
- Modify the meta-encodings of x86 SIMD instructions to use `infer_rex()`, mostly through the `enc_both_inferred()` helper
- Fix up tests that previously always emitted a REX prefix
2020-03-18 10:12:50 -07:00
Andrew Brown
f12fb29ae1 Add initial SIMD memory filetests 2020-03-17 19:37:55 -07:00
Andrew Brown
e1d3930ce4 Add SIMD store_complex 2020-03-17 19:37:55 -07:00
Andrew Brown
368094a95b Add SIMD load_complex 2020-03-17 19:37:55 -07:00
Andrew Brown
bda9d7cfa6 Add SIMD copy_to_ssa 2020-03-17 19:37:55 -07:00
Alex Crichton
4c3c717698 Update the filecheck dependency (#1348)
Removes an edge towards the `synstructure` dependency in our dependency
graph which, if removed entirely, is hoped to reduce build times locally
and on CI as you switch between `cargo build` and `cargo test` because
deep dependencies like `syn` won't have their features alternating back
and forth.
2020-03-17 15:33:54 -05:00
Andrew Brown
8598295bc4 Remove FPR32; fixes #1303
Until #1306 is resolved (some spilling/regalloc issue with larger FPR register banks), this removes FPR32 support. Only Wasm's `i64x2.mul` was using this register class and that instruction is predicated on AVX512 support; for the time being, that instruction will have to make do with the 16 FPR registers.
2020-03-17 12:46:41 -07:00
Nathan Froyd
af709ded94 bump cranelift version to 0.60.0 (#1328) 2020-03-17 15:29:20 -04:00
Andrew Brown
a2d388b593 Fix types of SIMD or, xor, and
The operands of these bitwise instructions could have different types and still be valid Wasm (i.e. `v128`). Because of this, we must tell Cranelift to cast both operands to the same type--the default type, in this case. This undoes the work merged in https://github.com/bytecodealliance/cranelift/pull/1233.
2020-03-17 11:44:25 -07:00
Andrew Brown
ebaf95e507 Fix types of i8x16 and i16x8 replace_lane
Because the smallest Wasm scalar type is i32, users of the `i8x16.replace_lane` and `i16x8.replace_lane` instructions will only be able to pass `i32` values as operands. These values must be reduced by dropping the upper bits (see https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#replace-lane-value) using Cranelift's `ireduce` instruction.
2020-03-17 11:44:25 -07:00
Andrew Brown
27532410d2 Fix local.set and local.tee types for SIMD
Because Wasm SIMD vectors store their type as `v128`, there is a mismatch between the more specific types Cranelift uses and Wasm SIMD. Because of this mismatch, Wasm SIMD translates to the default Cranelift type `I8X16`, causing issues when more specific type information is available (e.g. `I32x4`). To fix this, all incoming values to SIMD instructions are checked during translation (not runtime) and if necessary cast from `I8X16` to the appropriate type by functions like `optionally_bitcast_vector`, `pop1_with_bitcast` and `pop2_with_bitcast`. However, there are times when we must also cast to `I8X16` for outgoing values, as with `local.set` and `local.tee`.

There are other ways of resolving this (e.g., see adding a new vector type, https://github.com/bytecodealliance/cranelift/pull/1251) but we discussed staying with this casting approach in https://github.com/bytecodealliance/wasmtime/issues/1147.
2020-03-17 11:44:25 -07:00
Pat Hickey
8bbf07c758 Merge pull request #1327 from bjorn3/linkage_hidden
Add support for hidden visibility
2020-03-17 11:34:41 -07:00
Pat Hickey
9e57532098 Merge pull request #1311 from bytecodealliance/pch/cranelift_module_errors
cranelift-{module, faerie}: minor improvements to error reporting
2020-03-17 10:56:05 -07:00
Andrew Brown
ffa467a0d0 Translate Wasm's f32x4.convert_i32x4s to Cranelift's fcvt_from_sint 2020-03-17 10:52:03 -07:00
Andrew Brown
444d021ede Add x86 implementation of fcvt_from_sint 2020-03-17 10:52:03 -07:00
bjorn3
b4562c62e3 Add support for hidden visibility 2020-03-17 17:51:12 +01:00
Pat Hickey
2b87db3f55 cranelift-faerie: upgrade to faerie 0.15.0, fix error reporting
the `FaerieProduct` exposes faerie-specific types, so we can give
the `faerie::ArtifactError` on those methods.

`ModuleError::Backend` now expects an `anyhow::Error`, so we change
a .to_string into .into() and retain better error information.
2020-03-17 09:44:33 -07:00
Pat Hickey
fdfda89d59 cranelift-module: make backend error an anyhow::Error
This allows us to retain richer information from backend errors.
We already have `anyhow` as a dep in several places in the wasmtime
tree, and in cranelift-faerie. faerie is the only user of this
variant.

Existing code that puts a String into the Backend error can trivially
adapt their code to emit an anyhow::Error.
2020-03-17 09:44:33 -07:00
Samrat Man Singh
50496efb6b [cranelift] Fix block and value names in IR documentation 2020-03-17 11:47:59 +01:00
Samrat Man Singh
66aec23a0b Fix typo in comment (#1324) 2020-03-14 13:56:38 +01:00
Alex Crichton
65e32b3660 Store module name on wasmtime_environ::Module (#1309)
* Store module name on `wasmtime_environ::Module`

This keeps all name information in one place so we dont' have to keep
extra structures around in `wasmtime::Module`.

* rustfmt
2020-03-13 17:51:10 -05:00
Yury Delendik
f76b36f737 Write .debug_frame information (#53)
* Write .debug_frame information

* mv map_reg
2020-03-11 10:22:51 -05:00
Till Schneidereit
8f824a9fc1 Update outdated references to the Cranelift repository
This patch updates or removes all references to the Cranelift repository. It affects links in README documents, issues that were transferred to the Wasmtime repository, CI badges, and a small bunch of sundry items.
2020-03-09 14:06:24 +01:00
Andrew Brown
4284491339 Translate Wasm swizzle to Cranelift swizzle 2020-03-06 15:49:53 -08:00
Andrew Brown
fa7481a681 Add x86 implementation of SIMD swizzle instruction 2020-03-06 15:49:53 -08:00
Andrew Brown
4a0f53464a Remove '%test_' prefix from SIMD filetests 2020-03-06 14:57:11 -08:00
Andrew Brown
d19f727850 Refactor SIMD filetests to use a common naming convention
All filetests now should look like `simd-[instruction category]-[test type]`, where `[test type]` is something like `run` or `binemit`.
2020-03-06 14:57:11 -08:00
Andrew Brown
442edf5c84 Refactor SIMD legalizations to separate define* function
See https://github.com/bytecodealliance/wasmtime/issues/1168
2020-03-06 14:57:11 -08:00
Andrew Brown
6e0401b83a Refactor SIMD lane instructions to separate define* function 2020-03-06 14:57:11 -08:00
Andrew Brown
55337abd3f Move filetest misplaced during repo merge 2020-03-06 12:40:27 -08:00
Andrew Brown
7f7196a655 Add i64x2 integer multiplication using AVX512DQ 2020-03-06 10:53:22 -08:00
Andrew Brown
7d5075a649 Rename RexRecipeKind to RecipePrefixKind 2020-03-06 10:53:22 -08:00
Andrew Brown
2216f90916 Add an EVEX recipe (and associated recipe infrastructure) for encoding a binary operation 2020-03-06 10:53:22 -08:00
Andrew Brown
965714d675 Add encoding functions for emitting EVEX formats
Only the `reg, vvvv, rm` form is currently supported but it should not be difficult to add more forms.
2020-03-06 10:53:22 -08:00
Andrew Brown
079fcafcb1 Expand x86 registers to include 32 XMM registers
The EVEX encoding format (e.g. in AVX-512) allows addressing 32 registers instead of 16. The FPR register class currently defines 16 registers, `%xmm0`-`%xmm15`; that class is kept as-is with this change. A larger class, FPR32, is added as a super-class of FPR using a larger bank of registers, `%xmm0`-`%xmm31`.
2020-03-06 10:53:22 -08:00
Andrew Brown
1d15054310 Remove the debug crate's hard-coded dependency on register ordering 2020-03-06 10:53:22 -08:00
Andrew Brown
3f53bcb740 Remove dependency on hard-coded ordering of x86 register banks
With this change, register banks can now be re-ordered and other components (e.g. unwinding, regalloc) will no longer break. The previous behavior assumed that GPR registers always started at `RegUnit` 0.
2020-03-06 10:53:22 -08:00
Andrew Brown
518c7526d2 Fix incorrect register calculation in RegBank::unit_by_name 2020-03-06 10:53:22 -08:00
Andrew Brown
2c41648471 Wire up AVX-related settings with runtime detection in cranelift-native 2020-03-06 10:53:22 -08:00
Andrew Brown
baf71f5a5f Add AVX-related settings
Many more settings are possible but this subset is required in order to distinguish instructions that can use EVEX encodings.
2020-03-06 10:53:22 -08:00
Pat Hickey
e47de6f605 Merge pull request #1214 from froydnj/trap-exposure
cranelift-module: expose trap information when defining functions
2020-03-05 14:17:19 -08:00
Alex Crichton
3179dcf6f1 Update Cranelift's documentation after the merger. (#1238)
Update the documentation for the merger, and also for various changes in
Cranelift. Remove some old obsolete documentation, and convert the remaining
Sphinx files to Markdown. Some of the remaining content is still out of
date, but this is a step forward.
2020-03-05 15:51:12 -06:00
Nathan Froyd
2bb3096342 change interfaces to use slices instead of Vec 2020-03-05 10:19:01 -05:00
Ryan Hunt
4aa8776a9b Skip non-branching blocks now that we're using basic blocks
This is a rebase of [1]. In the long term, we'll want to simplify these
analysis passes. For now, this is simple and will reduce the number of
instructions processed in certain cases.

[1] https://github.com/bytecodealliance/cranelift/pull/866
2020-03-05 16:11:13 +01:00
Ryan Hunt
07f335dca6 Rename 'an block' to 'a block'
Missed this in the automatic rename of 'Ebb' to 'Block'.
2020-03-03 13:21:13 -06:00
Nathan Froyd
0f49a830c9 cranelift-module: expose trap information when defining functions
The current interface of `cranelift-module` requires consumers who want
to be informed about traps to discover that information through
`Module::Product`, which is backend-specific.  Since it's advantageous
to manipulate this information in a backend-agnostic way, this patch
changes `Module::define_function{,_bytes}` to return information about
the traps contained in the function being defined.
2020-03-03 11:37:15 -05:00
Darin Morrison
d68437e1e6 Update SIMD tests to use hex literals 2020-03-02 08:28:59 -08:00
Darin Morrison
c459579396 Add tests for hex parsing 2020-03-02 08:28:59 -08:00