Commit Graph

11151 Commits

Author SHA1 Message Date
Alex Crichton
d45cbba83f Add egraph cprop optimizations for splat (#6148)
This commit adds constant-propagation optimizations for
`splat`-of-constant to produce a `vconst` node. This should help later
hoisting these constants out of loops if it shows up in wasm.
2023-04-05 16:10:45 +00:00
Alex Crichton
3275c45993 Use an unaligned write for resolving libcall relocations (#6147)
This commit changes resolution of libcall relocations from writing a
`usize` into a raw pointer to specifically performing an unaligned
write. The addresses of libcalls to write to are not guaranteed to be
aligned, so this could technically have caused issues on some platforms
perhaps.

This was discovered now that Rust nightly will panic on unaligned writes
to pointers, and fuzzing ran into this case when compiled with a more
recent Nightly build.
2023-04-05 15:28:18 +00:00
Kevin Rizzo
3a92aa3d0a winch: Initial integration with wasmtime (#6119)
* Adding in trampoline compiling method for ISA

* Adding support for indirect call to memory address

* Refactoring frame to externalize defined locals, so it removes WASM depedencies in trampoline case

* Adding initial version of trampoline for testing

* Refactoring trampoline to be re-used by other architectures

* Initial wiring for winch with wasmtime

* Add a Wasmtime CLI option to select `winch`

This is effectively an option to select the `Strategy` enumeration.

* Implement `Compiler::compile_function` for Winch

Hook this into the `TargetIsa::compile_function` hook as well. Currently
this doesn't take into account `Tunables`, but that's left as a TODO for
later.

* Filling out Winch append_code method

* Adding back in changes from previous branch

Most of these are a WIP. It's missing trampolines for x64, but a basic
one exists for aarch64. It's missing the handling of arguments that
exist on the stack.

It currently imports `cranelift_wasm::WasmFuncType` since it's what's
passed to the `Compiler` trait. It's a bit awkward to use in the
`winch_codegen` crate since it mostly operates on `wasmparser` types.
I've had to hack in a conversion to get things working. Long term, I'm
not sure it's wise to rely on this type but it seems like it's easier on
the Cranelift side when creating the stub IR.

* Small API changes to make integration easier

* Adding in new FuncEnv, only a stub for now

* Removing unneeded parts of the old PoC, and refactoring trampoline code

* Moving FuncEnv into a separate file

* More comments for trampolines

* Adding in winch integration tests for first pass

* Using new addressing method to fix stack pointer error

* Adding test for stack arguments

* Only run tests on x86 for now, it's more complete for winch

* Add in missing documentation after rebase

* Updating based on feedback in draft PR

* Fixing formatting on doc comment for argv register

* Running formatting

* Lock updates, and turning on winch feature flags during tests

* Updating configuration with comments to no longer gate Strategy enum

* Using the winch-environ FuncEnv, but it required changing the sig

* Proper comment formatting

* Removing wasmtime-winch from dev-dependencies, adding the winch feature makes this not necessary

* Update doc attr to include winch check

* Adding winch feature to doc generation, which seems to fix the feature error in CI

* Add the `component-model` feature to the cargo doc invocation in CI

To match the metadata used by the docs.rs invocation when building docs.

* Add a comment clarifying the usage of `component-model` for docs.rs

* Correctly order wasmtime-winch and winch-environ in the publish script

* Ensure x86 test dependencies are included in cfg(target_arch)

* Further constrain Winch tests to x86_64 _and_ unix

---------

Co-authored-by: Alex Crichton <alex@alexcrichton.com>
Co-authored-by: Saúl Cabrera <saulecabrera@gmail.com>
2023-04-05 00:32:40 +00:00
Jamey Sharp
81545c3a86 Revert "simple_gvn: recognize commutative operators (#6135)" (#6142)
This reverts commit c85bf27ff8.
2023-04-04 20:22:44 +00:00
Karl Meakin
57e42d0c46 ISLE: rewrite loose inequalities to strict inequalities and strict inequalities to equalities (#6130)
* ISLE: rewrite loose inequalities to strict inequalities

* Rewrite strict inequalities to equalities where possible
2023-04-04 17:42:19 +00:00
Jimmy Bourassa
c35c047fc3 Derive Copy on wasmtime::ValType (#6138)
`ValType` is small enough that it can be copiable. Doing so means
Copy types can embed a `ValType` in them.

The need for this came up in this Wasmtime Ruby PR:
https://github.com/bytecodealliance/wasmtime-rb/pull/158
2023-04-04 16:49:00 +00:00
Jan-Justin van Tonder
c475735f5e cranelift-interpreter: Fix incorrect scalar_to_vector result (#6133)
* The `vectorizelanes` function performs a check to see whether there
is a single value provided in an array, and if so returns it as a
scalar.

While elsewhere in the interpreter this behaviour is relied
upon, it yields an incorrect result when attempting to convert a
scalar to a vector.

The original `vectorizelanes` remains untouched, however, an
unconditional variant `vectorizelanes_all` was added.

* A test was added under `filetests/runtests/issue5911.clif`.

Fixes #5911
2023-04-04 12:14:16 +00:00
Karl Meakin
c85bf27ff8 simple_gvn: recognize commutative operators (#6135)
* simple_gvn: recognize commutative operators

Normalize instructions with commutative opcodes by sorting the arguments. This
means instructions like `iadd v0, v1` and `iadd v1, v0` will be considered
identical by GVN and deduplicated.

* Remove `UsubSat` and `SsubSat` from `is_commutative`

They are not actually commutative

* Remove `TODO`s

* Move InstructionData normalization into helper fn

* Add normalization of commutative instructions in the epgrah implementation

* Handle reflexive icmp/fcmps in GVN

* Change formatting of `normalize_in_place`

* suggestions from code review
2023-04-04 00:25:05 +00:00
Pat Hickey
bf1aaba06d add supply chain audits for #5929's rustls changes (#6137)
The `ring` crate needed to be exempted: it contains a large quantity of asm and native binary implementations of crypto primitives. It is a major undertaking to certify the safety of those implementations.

ring also pulled in the wasm-bindgen family of crates for its wasm32-unknown-unknown target, which this project will not be using. Because we don't care about that platform, I added exemptions for all of these crates, so we don't have to audit them.

The actual supply chain audits for rusttls, rustls-webpki, sct, and tokio-rustls were unremarkable. I also audited a small diff on wasm-bindgen-shared because it was trivial.
2023-04-03 22:19:23 +00:00
Pat Hickey
689f07cb79 cargo-deny: allow the MPL-2.0 and OpenSSL licenses (#6136)
* cargo-deny: allow the MPL-2.0 and OpenSSL licenses

These are required in order to merge https://github.com/bytecodealliance/wasmtime/pull/5929.

* deny.toml: add clarification of license for `ring`
2023-04-03 22:13:21 +00:00
Karl Meakin
c8c224ead6 ISLE: move icmp rewrites to separate file. (#6120)
* ISLE: move `icmp` rewrites to separate file.

Move `icmp`-related rewrite rules from `algebraic.isle` to `icmp.isle`.
Also move `icmp`-related tests from `algebraic.clif` to `icmp.clif`.

* Put parameterized and unparameterized `icmp` tests in separate files

* Undo refactoring of (ir)reflexivity rewrites

* Fix `icmp-parameterised.clif`

* Undo formatting/comment changes
2023-03-31 17:40:31 +00:00
Pat Hickey
83d00fea4a cargo vet remaining dependencies for #5929 (#6125) 2023-03-30 17:30:59 +00:00
Yoni L
94f2ff0921 cranelift::codegen::Context::optimize(): reduce verbosity of "egraph stats" traces (#6122) 2023-03-30 00:46:14 +00:00
Pat Hickey
3d03729fa1 wasi-http supply chain audit (#6121)
* add cargo-deny exception for duplicate versions of windows-sys

* cargo vetting for all new deps introduced by https://github.com/bytecodealliance/wasmtime/pull/5929

The audits are straightforward. The exemptions, as always, need to be justified:

* core-foundation, core-foundation-sys, security-framework, security-framework-sys: these are large crates which are FFI bindings to Mac OS frameworks. As such they contain tons of unsafe code to make these FFI calls and manage memory. These crates are too big to audit.

* schannel: same as the above, except this is a windows component, which I'm also unfamiliar with.

* openssl, openssl-sys: also large FFI bindings which are impractical to audit.

* futures-macro, futures-task: while not as complex as futures-util, these are beyond my personal understanding of futures to vet practically. I've asked Alex to look at auditing these, and he will after he returns from vacation next week.

* futures-util: 25kloc of code, over 149 instances of the substring "unsafe" (case insensitive), this is impractical to audit in the extreme.

* h2, http, httparse, hyper, mio, tokio: this so-called tokio/hyper family are very large and challenging to audit. Bobby Holley has indicated that he is working to get the AWS engineers who maintain these crates to publish their own audits, which we can then import. We expect to exempt these until those imports are available.
2023-03-30 00:29:07 +00:00
Roman Volosatovs
c10e804617 feat(wit-bindgen): relax Sized bound on Host traits (#6117)
This allows to use implementations as trait objects
(e.g. `Box<dyn myiface::Host>`)

Signed-off-by: Roman Volosatovs <roman@profian.com>
2023-03-29 18:30:54 +00:00
Alex Crichton
0b0ac3ff73 x64: Add AVX support for some more float-related instructions (#6092)
* x64: Add AVX encodings of `vcvt{ss2sd,sd2ss}`

Additionally update the instruction helpers to take an `XmmMem` argument
to allow load sinking into the instruction.

* x64: Add AVX encoding of `sqrts{s,d}`

* x64: Add AVX support for `rounds{s,d}`
2023-03-29 18:09:49 +00:00
Alex Crichton
afb417920d x64: Deduplicate fcmp emission logic (#6113)
* x64: Deduplicate fcmp emission logic

The `select`-of-`fcmp` lowering duplicated a good deal of `FloatCC`
lowering logic that was already done by `emit_fcmp`, so this commit
refactors these lowering rules to instead delegate to `emit_fcmp` and
then handle that result.

* Swap order of condition codes

Shouldn't affect the correctness of this operation and it's a bit more
natural to write the lowering rule this way.

* Swap the order of comparison operands

No need to swap `a b`, only the `x y` needs swapping.

* Fix x64 printing of `XmmCmove`
2023-03-29 16:24:25 +00:00
Karl Meakin
dcf0ea9ff3 ISLE: rewrite and/or of icmp (#6095)
* ISLE: rewrite `and`/`or` of `icmp`

* Add `make-icmp-tests.sh` script

* Remove unused changes
2023-03-29 00:13:27 +00:00
Jamey Sharp
01b82adf0d Use GitHub teams as code owners (#6114)
The teams named in this revised version of the `CODEOWNERS` file are
currently configured with the same members as are listed in the file
now.

We wanted a single member of the selected team to be assigned as a
reviewer, but listing people explicitly in CODEOWNERS causes all the
named people to be assigned. Using teams instead allows us to configure
the load-balancing policy.

This also will allow us to add and remove reviewers without needing a PR
every time.
2023-03-28 23:10:39 +00:00
Karl Meakin
97d9f77d94 Add precise_output argument to test optimize. (#6111)
* Add `precise_output` argument to `test optimise`.

Also allow optimise tests to be updated by `CRANELIFT_TEST_BLESS=1`

* Move `check_precise_output` and `update_test` to `subtest`
2023-03-28 22:32:04 +00:00
Saúl Cabrera
af4d94c85a winch(x64): Initial implementation for function calls (#6067)
* winch(x64): Initial implementation for function calls

This change adds the main building blocks for calling locally defined
functions. Support for function imports will be added iteratively after this
change lands and once trampolines are supported.

To support function calls, this change introduces the following functionality to
the MacroAssembler:

* `pop` to pop the machine stack into a given register, which in the case of
this change, translates to the x64 pop instruction.

* `call` to a emit a call to locally defined functions.

* `address_from_sp` to construct memory addresses with the SP as a base.

* `free_stack` to emit the necessary instrunctions to claim stack space.

The heavy lifting of setting up and emitting the function call is done through
the implementation of `FnCall`.

* Fix spill behaviour in function calls and add more documentation

This commits adds a more detailed documentation to the `call.rs` module.

It also fixes a couple of bugs, mainly:

* The previous commit didn't account for memory addresses used as arguments for
the function call, any memory entry in the value stack used as a function
argument should be tracked and then used to claim that memory when the function
call ends. We could `pop` and do this implicitly, but we can also track this
down and emit a single instruction to decrement the stack pointer, which will
result in better code.

* Introduce a differentiator between addresses relative or absolute to the stack
pointer. When passing arguments in the stack -- assuming that SP at that point
is aligned for the function call -- we should store the arguments relative to
the absolute position of the stack pointer and when addressing a memory entry in
the Wasm value stack, we should use an address relative to the offset and the
position of the stack pointer.

* Simplify tracking of the stack space needed for emitting a function call
2023-03-28 18:30:31 +00:00
Jamey Sharp
d54c00ba4d Initial designation of code owners (#6084)
We want to make sure every contributor gets some kind of meaningful
response in a timely fashion. To that end, this PR configures GitHub to
auto-assign somebody to every newly-opened PR.

People must only be added to this file if they've agreed to this
obligation. The details of what's expected are listed in the file. I'll
only merge this if it's signed off by everyone listed in this initial
version.
2023-03-28 18:13:34 +00:00
Peter Huene
73f42bf817 Fix export translation for components. (#6108)
* Fix export translation for components.

Exports in the component model cause a new index to be added to the index space
of the item being exported.

This commit updates component translation so that translation of component
export sections properly updates internal lists representing those index
spaces.

* Code review feedback.
2023-03-28 00:18:48 +00:00
Bobby Holley
82fcf3e562 Bump cargo-vet to 0.6.1 (#6110)
* Bump cargo-vet to 0.6.1.

* Add Fuchsia and prune.
2023-03-28 00:07:14 +00:00
Maja Kądziołka
db07988ccb x64: emit_cmp: use x64_test for comparisons with 0 (#6086)
* x64: emit_cmp: use x64_test for comparisons with 0

See #5869

* fixup! x64: emit_cmp: use x64_test for comparisons with 0
2023-03-27 15:38:48 +00:00
Afonso Bordado
dd9804514d CI: Upgrade QEMU to 7.2.0 (#6102)
* ci: Update QEMU to 7.2.0

* ci: Drop QEMU madvise patch

This seems to have been upstreamed in:
https://lists.gnu.org/archive/html/qemu-devel/2022-06/msg03752.html

Running the full CI to ensure this works on all arches.
prtest:full
2023-03-26 21:44:39 +00:00
Afonso Bordado
a002a2cc5e riscv64: Add instruction helpers (#6099)
* riscv64: Add helpers for `add`

* riscv64: Add helpers for `sub`

* riscv64: Add helpers for `sll`

* riscv64: Add helpers for `srl`

* riscv64: Add helpers for `sra`

* riscv64: Add helpers for `or`

* riscv64: Add helpers for `and`

* riscv64: Add helpers for `xor`

* riscv64: Add helpers for `addi`

* riscv64: Add helpers for `slli`

* riscv64: Add helpers for `srli`

* riscv64: Add helpers for `srai`

* riscv64: Add helpers for `ori`

* riscv64: Add helpers for `xori`

* riscv64: Add helpers for `andi`

* riscv64: Add helpers for `not`

* riscv64: Add helpers for `sltiu`

* riscv64: Add helpers for `seqz`

* riscv64: Add helpers for `addw`

* riscv64: Add helpers for `subw`

* riscv64: Add helpers for `sllw`

* riscv64: Add helpers for `slliw`

* riscv64: Add helpers for `srlw`

* riscv64: Add helpers for `srliw`

* riscv64: Add helpers for `sraw`

* riscv64: Add helpers for `sraiw`

* riscv64: Add helpers for `sltu`

* riscv64: Add helpers for `mul`

* riscv64: Add helpers for `mulh`

* riscv64: Add helpers for `mulhu`

* riscv64: Add helpers for `div`

* riscv64: Add helpers for `divu`

* riscv64: Add helpers for `rem`

* riscv64: Add helpers for `remu`

* riscv64: Add helpers for `mulw`

* riscv64: Add helpers for `divw`

* riscv64: Add helpers for `divuw`

* riscv64: Add helpers for `remw`

* riscv64: Add helpers for `remuw`

* riscv64: Add helpers for `neg`

* riscv64: Add helpers for `addiw`

* riscv64: Add helpers for `sext.w`

* riscv64: Add helpers for `fadd`

* riscv64: Add helpers for `fsub`

* riscv64: Add helpers for `fmul`

* riscv64: Add helpers for `fdiv`

* riscv64: Add helpers for `fsqrt`

* riscv64: Add helpers for `fmadd`

* riscv64: Add helpers for `fsgnj`

* riscv64: Add helpers for `fsgnjn`

* riscv64: Add helpers for `fsgnjx`

* riscv64: Add helpers for `fcvtds`

* riscv64: Add helpers for `fcvtsd`

* riscv64: Add helpers for `adduw`

* riscv64: Add helpers for `zext.w`

* riscv64: Add helpers for `andn`

* riscv64: Add helpers for `orn`

* riscv64: Add helpers for `clz`

* riscv64: Add helpers for `clzw`

* riscv64: Add helpers for `ctz`

* riscv64: Add helpers for `ctzw`

* riscv64: Add helpers for `cpop`

* riscv64: Add helpers for `max`

* riscv64: Add helpers for `feq`

* riscv64: Add helpers for `flt`

* riscv64: Add helpers for `fle`

* riscv64: Add helpers for `fgt`

* riscv64: Add helpers for `fge`

* riscv64: Add helpers for `sext.b`

* riscv64: Add helpers for `sext.h`

* riscv64: Add helpers for `zext.h`

* riscv64: Add helpers for `rol`

* riscv64: Add helpers for `rolw`

* riscv64: Add helpers for `ror`

* riscv64: Add helpers for `rorw`

* riscv64: Add helpers for `rev8`

* riscv64: Add helpers for `brev8`

* riscv64: Add helpers for `bseti`

* riscv64: Add helpers for `pack`

* riscv64: Add helpers for `packw`

* riscv64: Add helpers for `slli.uw`

* riscv64: Add helpers for `fabs`

* riscv64: Add helpers for `fneg`
2023-03-24 18:01:04 +00:00
Nathan Whitaker
c3decdf910 cranelift: Implement TLS on aarch64 Mach-O (Apple Silicon) (#5434)
* Implement TLS on Aarch64 Mach-O

* Add aarch64 macho TLS filetest

* Address review comments

- `Aarch64` instead of `AArch64` in comments
- Remove unnecessary guard in tls_value lowering
- Remove unnecessary regalloc metadata in emission

* Use x1 as temporary register in emission

- Instead of passing in a temporary register to use when emitting
the TLS code, just use `x1`, as it's already in the clobber set.
This also keeps the size of `aarch64::inst::Inst` at 32 bytes.
- Update filetest accordingly

* Update aarch64 mach-o TLS filetest
2023-03-24 17:54:01 +00:00
bjorn3
d0570a77ce Fix github-release action when the dev tag is missing (#6098)
There was a missing rest field access. In addition createTag doesn't actually create a tag, it creates a tag object. A tag object is an object which references a commit or other kind of object and has various kinds of metadata. You need to store it in a reference stored in refs/tags/ to actually show as tag in the git ui. The code to update the tag however creates a lightweight tag (which is a file in refs/tags/ which directly references a commit rather than a tag object) as such do the same when creating the initial dev tag by using createRef with a commit id as object sha.

See also https://git-scm.com/book/en/v2/Git-Internals-Git-References for the difference between a lightweight tag and an annotated tag.
2023-03-24 15:16:33 +00:00
Afonso Bordado
3546ccf7d1 riscv64: Cleanup unused lower_float_unordered (#6096) 2023-03-23 21:08:38 +00:00
Afonso Bordado
602ff71fe4 riscv64: Add Zba extension instructions (#6087)
* riscv64: Use `add.uw` to zero extend

* riscv64: Implement `add.uw` optimizations

* riscv64: Add `Zba` `iadd+ishl` optimizations

* riscv64: Add `shl+uextend` optimizations based on `Zba`

* riscv64: Fix some issues with `Zba` instructions

* riscv64: Restrict shnadd selection

* riscv64: Fix `extend` priorities

* riscv64: Remove redundant `addw` rule

* riscv64: Specify type for `add` extend rules

* riscv64: Use `u64_from_imm64` extractor instead of `uimm8`

* riscv64: Restrict `uextend` in `shnadd.uw` rules

* riscv64: Use concrete type in `slli.uw` rule

* riscv64: Add extra arithmetic extends tests

Co-authored-by: Jamey Sharp <jsharp@fastly.com>

* riscv64: Make `Adduw` types concrete

* riscv64: Add extra arithmetic extend tests

* riscv64: Add `sextend`+Arithmetic rules

* riscv64: Fix whitespace

* cranelift: Move arithmetic extends tests with i128 to separate file

---------

Co-authored-by: Jamey Sharp <jsharp@fastly.com>
2023-03-23 20:06:03 +00:00
Ulrich Weigand
6f66abd5c7 s390x: Improved TrapIf implementation (#6079)
Following up on the discussion in
https://github.com/bytecodealliance/wasmtime/pull/6011
this adds an improved implementation of TrapIf for s390x
using a single conditional branch instruction.

If the trap conditions is true, we branch into the middle of
the branch instruction - those middle two bytes are zero,
which matches the encoding of the trap instruction.

In addition, show the trap code for Trap and TrapIf
instructions in assembler output.
2023-03-23 14:50:43 +00:00
Saúl Cabrera
a6925c21c5 wasmtime: Make StoreContextMut accessible in epoch deadline callback (#6075)
This commit changes the signature of the `Store::epoch_deadline_callback` to
take in `StoreContextMut` instead of a mutable reference to the store's data.

This is useful in cases in which the callback definition needs access to the
Store to be able to use other methods that take in `AsContext`/`AsContextMut`,
like for example `WasmtimeBacktrace::capture`
2023-03-23 14:39:36 +00:00
Alex Crichton
2fde25311e x64: Refactor and fill out some gpr-vs-xmm bits (#6058)
* x64: Add instruction helpers for `mov{d,q}`

These will soon grow AVX-equivalents so move them to instruction helpers
to have clauses for AVX in the future.

* x64: Don't auto-convert between RegMemImm and XmmMemImm

The previous conversion, `mov_rmi_to_xmm`, would move from GPR registers
to XMM registers which isn't what many of the other `convert` statements
between these newtypes do. This seemed like a possible footgun so I've
removed the auto-conversion and added an explicit helper to go from a
`u32` to an `XmmMemImm`.

* x64: Add AVX encodings of some more GPR-related insns

This commit adds some more support for AVX instructions where GPRs are
in use mixed in with XMM registers. This required a few more variants of
`Inst` to handle the new instructions.

* Fix vpmovmskb encoding

* Fix xmm-to-gpr encoding of vmovd/vmovq

* Fix typo

* Fix rebase conflict

* Fix rebase conflict with tests
2023-03-22 14:58:09 +00:00
Afonso Bordado
a1072007b8 fuzzgen: Generate call_indirect instructions (#6077)
* fuzzgen: Add `call_indirect`

* fuzzgen: Assign `call` results to variables
2023-03-22 11:24:53 +00:00
Afonso Bordado
3957d577b7 fuzzgen: Fuzz ISA flags (#6001) 2023-03-22 11:09:00 +00:00
Juan Bono
1ed7c89e3d Add riscv64 backend to the README (#6085) 2023-03-22 02:29:19 +00:00
Afonso Bordado
7a3df7dcc0 riscv64: Improve ctz/clz/cls codegen (#5854)
* cranelift: Add extra runtests for `clz`/`ctz`

* riscv64: Restrict lowering rules for `ctz`/`clz`

* cranelift: Add `u64` isle helpers

* riscv64: Improve `ctz` codegen

* riscv64: Improve `clz` codegen

* riscv64: Improve `cls` codegen

* riscv64: Improve `clz.i128` codegen

Instead of checking if we have 64 zeros in the top half. Check
if it *is* 0, that way we avoid loading the `64` constant.

* riscv64: Improve `ctz.i128` codegen

Instead of checking if we have 64 zeros in the bottom half. Check
if it *is* 0, that way we avoid loading the `64` constant.

* riscv64: Use extended value in `lower_cls`

* riscv64: Use pattern matches on `bseti`
2023-03-21 23:15:14 +00:00
Karl Meakin
ff6f17ca52 ISLE: add synonyms for all variations of icmp (#6081) 2023-03-21 22:13:00 +00:00
Trevor Elliott
a24002508d Pick argument and return types based on opcode constraints (#5947)
* Pick argument and return types based on opcode constraints

Co-authored-by: Jamey Sharp <jsharp@fastly.com>

* Lazily build the OPCODE_SIGNATURES list

* Skip unsupported isplit/iconcat cases

* Add an issue reference for the isplit/iconcat exemption

* Refactor the deny lists to use exceptions!, and remove redundant entries

---------

Co-authored-by: Jamey Sharp <jsharp@fastly.com>
2023-03-21 21:52:42 +00:00
Alexa VanHattum
13be5618a7 Cranelift: ISLE: aarch64: fix imm12_from_negated_value for i32, i16 (#6078)
* Fix the semantics of imm12_from_negated_value, swapping to a partial term + rule

* wrapping_neg
2023-03-21 19:16:25 +00:00
uint256_t
59d46c2fec cranelift-entity: improve EntitySet::cardinality() implementation (#6066)
* Simplify 'EntitySet::cardinality()'

* Fix test
2023-03-21 18:59:54 +00:00
Alexa VanHattum
1dca793ced Add partial keyword to ISLE reference (#6076)
Noticed this was missing, tried to add based on the comments in https://github.com/bytecodealliance/wasmtime/pull/5392 (CC @jameysharp)
2023-03-21 18:41:33 +00:00
Trevor Elliott
861220c433 Restrict the types for isplit and iconcat to match backends (#6070)
* Restrict the types for isplit and iconcat to match backends

* Admit unimplemented bitwidths to isplit/iconcat

* Modify the NarrowInt type instead of shadowing it

* Fix filetest failures
2023-03-21 01:21:00 +00:00
Karl Meakin
7d9318fe77 cranelift: rewrite iabs(ineg(x)) and iabs(iabs(x)) (#6072)
* cranelift: rerwite `iabs(ineg(x))`` and `iabs(iabs(x))`

* Fix comment on `iabs(iabs(x))` rewrite

* Remove subsume on rewrite for `iabs(ineg(x))`
2023-03-21 00:12:21 +00:00
Alex Crichton
a3b21031d4 Add a MachBuffer::defer_trap method (#6011)
* Add a `MachBuffer::defer_trap` method

This commit adds a new method to `MachBuffer` to defer trap opcodes to
the end of a function in a similar manner to how constants are deferred
to the end of the function. This is useful for backends which frequently
use `TrapIf`-style opcodes. Currently a jump is emitted which skips the
next instruction, a trap, and then execution continues normally. While
there isn't any pressing problem with this construction the trap opcode
is in the middle of the instruction stream as opposed to "off on the
side" despite rarely being taken.

With this method in place all the backends (except riscv64 since I
couldn't figure it out easily enough) have a new lowering of their
`TrapIf` opcode. Now a trap is deferred, which returns a label, and then
that label is jumped to when executing the trap. A fixup is then
recorded in `MachBuffer` to get patched later on during emission, or at
the end of the function. Subsequently all `TrapIf` instructions
translate to a single branch plus a single trap at the end of the
function.

I've additionally further updated some more lowerings in the x64 backend
which were explicitly using traps to instead use `TrapIf` where
applicable to avoid jumping over traps mid-function. Other backends
didn't appear to have many jump-over-the-next-trap patterns.

Lots of tests have had their expectations updated here which should
reflect all the traps being sunk to the end of functions.

* Print trap code on all platforms

* Emit traps before constants

* Preserve source location information for traps

* Fix test expectations

* Attempt to fix s390x

The MachBuffer was registering trap codes with the first byte of the
trap, but the SIGILL handler was expecting it to be registered with the
last byte of the trap. Exploit that SIGILL is always represented with a
2-byte instruction and always march 2-backwards for SIGILL, continuing
to march backwards 1 byte for SIGFPE-generating instructions.

* Back out s390x changes

* Back out more s390x bits

* Review comments
2023-03-20 21:24:47 +00:00
Alex Crichton
6a03398faf Speed up index fetches on CI (#6069)
* Speed up index fetches on CI

Use the `sparse` protocol from Rust 1.68.0 which should shave a minute
or two off most steps on CI.

* Update nightly toolchains in CI

prtest:full

* Fix date
2023-03-20 19:44:59 +00:00
bjorn3
49bab6db7f Ensure the sequence number doesn't leak out of Layout (#6061)
Previously it could affect the PartialEq and Hash impls. Ignoring the
sequence number in PartialEq and Hash allows us to not renumber all
blocks in the incremental cache.
2023-03-20 19:20:00 +00:00
bjorn3
fc3c5d2414 Properly use the VersionMarker in CachedFunc (#6062) 2023-03-20 19:18:51 +00:00
Alex Crichton
dd7fa81b20 x64: Run more filetests with AVX support (#6063)
This commit goes through the `runtests` folder of the `filetests`
test suite and ensure that everything which uses simd or float-related
instructions on x64 is executed with the baseline support for x86_64 in
addition to adding in AVX support. Most of the instructions used have
AVX equivalents so this should help test all of the equivalents in
addition to the codegen filetests in the x64 folder.
2023-03-20 19:13:14 +00:00