Commit Graph

1364 Commits

Author SHA1 Message Date
Alex Crichton
c6b095f9a3 cranelift: Implement nan canonicalization for vectors (#3146)
This fixes some fuzz bugs that came about enabling simd where nan
canonicalization is performed on the fuzzers but cranelift would panic
on these ops for vectors. This adds some custom codegen with `bitselect`
to ensure any nan lanes are canonical-nan lanes in the canonicalized
operations.
2021-08-05 13:44:16 -05:00
Alex Crichton
9e142f8792 Fix some warnings on nightly Rust (#3148)
Looks like these trailing-semicolons-in-macros are likely to become a
hard error in the future, so this updates to remove them as necessary.
2021-08-05 13:02:44 -05:00
Alex Crichton
4cfa031c5f Implement API support for v128-globals (#3147)
Found via fuzzing, and looks like these were accidentally left out along
the way SIMD was taking shape.
2021-08-05 13:02:34 -05:00
Alex Crichton
a33caec9be Bump the wasm-tools crates (#3139)
* Bump the wasm-tools crates

Pulls in some updates here and there, mostly for updating crates to the
latest version to prepare for later memory64 work.

* Update lightbeam
2021-08-04 09:53:47 -05:00
Sam Parker
3bc2f0c701 Enable simd_X_extadd_pairwise_X for AArch64
Lower to [u|s]addlp for AArch64.

Copyright (c) 2021, Arm Limited.
2021-08-03 10:25:09 +01:00
Chris Fallin
a13a777230 Bump to Wasmtime v0.29.0 and Cranelift 0.76.0. 2021-08-02 11:24:09 -07:00
Alex Crichton
63a3bbbf5a Change VMMemoryDefinition::current_length to usize (#3134)
* Change VMMemoryDefinition::current_length to `usize`

This commit changes the definition of
`VMMemoryDefinition::current_length` to `usize` from its previous
definition of `u32`. This is a pretty impactful change because it also
changes the cranelift semantics of "dynamic" heaps where the bound
global value specifier must now match the pointer type for the platform
rather than the index type for the heap.

The motivation for this change is that the `current_length` field (or
bound for the heap) is intended to reflect the current size of the heap.
This is bound by `usize` on the host platform rather than `u32` or`
u64`. The previous choice of `u32` couldn't represent a 4GB memory
because we couldn't put a number representing 4GB into the
`current_length` field. By using `usize`, which reflects the host's
memory allocation, this should better reflect the size of the heap and
allows Wasmtime to support a full 4GB heap for a wasm program (instead
of 4GB minus one page).

This commit also updates the legalization of the `heap_addr` clif
instruction to appropriately cast the address to the platform's pointer
type, handling bounds checks along the way. The practical impact for
today's targets is that a `uextend` is happening sooner than it happened
before, but otherwise there is no intended impact of this change. In the
future when 64-bit memories are supported there will likely need to be
fancier logic which handles offsets a bit differently (especially in the
case of a 64-bit memory on a 32-bit host).

The clif `filetest` changes should show the differences in codegen, and
the Wasmtime changes are largely removing casts here and there.

Closes #3022

* Add tests for memory.size at maximum memory size

* Add a dfg helper method
2021-08-02 13:09:40 -05:00
Johnnie Birch
e519fca61c Refactor and turn on lowering for extend-add-pairwise 2021-07-31 10:52:39 -07:00
Johnnie Birch
e373ddfe1b Add extend-add-pairwise instructions x64 2021-07-30 15:06:58 -07:00
Andrew Brown
26c78c06ef refactor: remove unused field
PR #3131 fixed the failing builds by allowing this field to be dead.
After looking at it further the field is not being used and can be
removedi completely.
2021-07-30 10:58:37 -07:00
Alex Crichton
4632b6a816 Fix warning on new-stable (#3131)
One of the fields of `TargetIsa` isn't used in the
cranelift-codegen-meta crate, but instead of refactoring to try to
remove it this just adds `#[allow(dead_code)]` for now in the assumption
that when the old backends go away this will probably go away as well.
2021-07-30 11:13:21 -05:00
Johnnie Birch
4f601edc36 Add x64 support for remaining int-to-int extend simd instructions
Adds remaming support for int to int extend simd instructions.
Specifically adds support for remaining I32x4->I64x2 instructions
2021-07-28 23:33:42 -07:00
Sam Parker
5eb2dca9f1 Added doc comment
And removed an accidental code move.

Copyright (c) 2021, Arm Limited.
2021-07-28 13:14:20 +01:00
Sam Parker
f2806a9192 rebase and ran cargo fmt
Copyright (c) 2021, Arm Limited.
2021-07-28 13:14:20 +01:00
Sam Parker
541a4ee428 Enable simd_extmul_* for AArch64
Lower simd_extmul_[low/high][signed/unsigned] to [s|u]widen inputs to
an imul node.

Copyright (c) 2021, Arm Limited.
2021-07-28 13:14:20 +01:00
Johnnie Birch
500f530322 Add support for i32x4_trunc_sat_f64x2_s for x64 2021-07-26 22:24:30 -07:00
Johnnie Birch
23290f0450 Add support for i32x4_trunc_sat_f64x2_u for x64 2021-07-26 22:24:30 -07:00
Johnnie Birch
5deda27977 Add support for Saturating Rounding Q-format Multiplication for x64 2021-07-26 20:32:46 -07:00
Johnnie Birch
ffec1f9b41 Fix for 3089 X64 ext_mul_i8x16 has incorrect lowering
Also factors out unnecessary temp register
2021-07-26 20:06:43 -07:00
Andrew Brown
766774e1f5 refactor: reorganize crate imports 2021-07-26 13:39:16 -07:00
Andrew Brown
6b86984c41 x64: avoid load-coalescing SIMD operations with non-aligned loads
Fixes #2943, though not as optimally as may be desired. With x64 SIMD
instructions, the memory operand must be aligned--this change adds that
check. There are cases, however, where we can do better--see #3106.
2021-07-26 13:39:16 -07:00
Nick Fitzgerald
a2cfddff9c Merge pull request #3116 from fitzgen/update-gimli-and-addr2line
Update `gimli` to 0.25; `addr2line` to 0.16
2021-07-26 13:01:37 -07:00
Chris Fallin
0f068ac933 Merge pull request #3117 from fitzgen/log-levels
cranelift: Move most debug-level logs to the trace level
2021-07-26 12:52:39 -07:00
Nick Fitzgerald
4283d2116d cranelift: Move most debug-level logs to the trace level
Cranelift crates have historically been much more verbose with debug-level
logging than most other crates in the Rust ecosystem. We log things like how
many parameters a basic block has, the color of virtual registers during
regalloc, etc. Even for Cranelift hackers, these things are largely only useful
when hacking specifically on Cranelift and looking at a particular test case,
not even when using some Cranelift embedding (such as Wasmtime).

Most of the time, when people want logging for their Rust programs, they do
something like:

    RUST_LOG=debug cargo run

This means that they get all that mostly not useful debug logging out of
Cranelift. So they might want to disable logging for Cranelift, or change it to
a higher log level:

    RUST_LOG=debug,cranelift=info cargo run

The problem is that this is already more annoying to type that `RUST_LOG=debug`,
and that Cranelift isn't one single crate, so you actually have to play
whack-a-mole with naming all the Cranelift crates off the top of your head,
something more like this:

    RUST_LOG=debug,cranelift=info,cranelift_codegen=info,cranelift_wasm=info,...

Therefore, we're changing most of the `debug!` logs into `trace!` logs: anything
that is very Cranelift-internal, unlikely to be useful/meaningful to the
"average" Cranelift embedder, or prints a message for each instruction visited
during a pass. On the other hand, things that just report a one line statistic
for a whole pass, for example, are left as `debug!`. The more verbose the log
messages are, the higher the bar they must clear to be `debug!` rather than
`trace!`.
2021-07-26 11:50:16 -07:00
Nick Fitzgerald
3d76cbdf34 Update gimli to 0.25; addr2line to 0.16 2021-07-26 11:04:53 -07:00
Afonso Bordado
a2fb019ba7 cranelift: Add basic i128 support in interpreter 2021-07-23 11:22:07 -07:00
Afonso Bordado
084383f60a cranelift: Add support for i128 values in DataValue 2021-07-23 11:22:07 -07:00
Afonso Bordado
3a38400447 aarch64: Refactor lower_icmp to use a single materialize_bool_result 2021-07-19 09:31:14 -07:00
Afonso Bordado
14d1c7ee9f aarch64: Refactor lower_icmp to allow returning a different flag 2021-07-19 09:31:14 -07:00
Afonso Bordado
e628fb376f aarch64: Fix incorrect code generation for overflow icmp in i16 values 2021-07-19 09:31:14 -07:00
Afonso Bordado
db5566dadb aarch64: Fix lowering amounts for shifts
This commit addresses two issues:
* A panic when shifting any non i128 type by i128 amounts (#3064)
* Wrong results when lowering shifts with small types (i8, i16)

In these types when shifting for amounts larger than the size of the
type, we would not get the wrapping behaviour that we see on i32 and i64.
This is because in these larger types, the wrapping behaviour is automatically
implemented by using the appropriate instruction, however we do not
have i8 and i16 specific instructions, so we have to manually wrap
the shift amount with an AND instruction.

This issue is also found on x86_64 and s390x, and a separate issue will
be filed for those.

Closes #3064
2021-07-16 22:08:02 +01:00
Anton Kirilov
6c3d7092b9 Enable the simd_conversions test for AArch64
Copyright (c) 2021, Arm Limited.
2021-07-16 22:04:45 +01:00
Johnnie Birch
2452a4cd74 Refactor lowering structure for ext_mul on x64 and add comments 2021-07-15 01:07:52 -07:00
Johnnie Birch
e5b6bee968 Add emit tests to ext_mul_* instructions 2021-07-15 01:07:52 -07:00
Johnnie Birch
6fbe0b72bd Add simd_extmul_* support for x64 2021-07-15 01:07:52 -07:00
Johnnie Birch
d8e813204e Fold fcvt_low_from_uinit into previously existing clif instructions 2021-07-09 10:39:05 -07:00
Johnnie Birch
6dd2df4fb3 Update comment on fcvt_low_from_sint instruction 2021-07-09 10:39:05 -07:00
Johnnie Birch
2d676d838f Implements f64x2.convert_low_i32x4_u for x64 2021-07-09 10:39:05 -07:00
Chris Fallin
c71ad9490e Merge pull request #3056 from afonso360/aarch64-fix-overflow-imm
aarch64: Fix incorrect encoding of large const values in icmp.
2021-07-03 16:05:49 -07:00
Afonso Bordado
eebae8d4c8 aarch64: Fix incorrect encoding of large const values in icmp.
When encoding constants as immediates into an RSE Imm12 instruction we need to take special care to check if the value that we are trying to input does not overflow its type when viewed as a signed value. (i.e. iconst.i8 200)

We cannot both put an immediate and sign extend it, so we need to lower it into a separate reg, and emit the sign extend into the instruction.

For more details see the [cg_clif bug report](https://github.com/bjorn3/rustc_codegen_cranelift/issues/1184#issuecomment-873214796).
2021-07-03 22:42:15 +01:00
bjorn3
37115c10e0 Implement Display for settings::Value 2021-07-03 14:34:42 +02:00
Benjamin Bouvier
4c595f4f9d Remove unused store_stackslot/load_stackslot trait methods. 2021-07-02 18:09:33 +02:00
Benjamin Bouvier
91c65d739f Remove unused code in machinst 2021-07-02 18:09:33 +02:00
Anton Kirilov
330f02aa09 Enable the simd_i32x4_trunc_sat_f64x2 test for AArch64
Also, reorganize the AArch64-specific VCode instructions for unary
narrowing and widening vector operations, so that they are more
straightforward to use.

Copyright (c) 2021, Arm Limited.
2021-06-30 12:17:53 +01:00
Anton Kirilov
98f1ac789e Enable the simd_i16x8_q15mulr_sat_s test on AArch64
Copyright (c) 2021, Arm Limited.
2021-06-28 12:24:31 +01:00
Chris Fallin
d42c8692bc x64 backend: be explicit about unimplemented opcodes.
As discussed in #3035, most backends have explicit
`unimplemented!(...)` match-arms for opcode lowering cases that are not
yet implemented; this allows the backend maintainer to easily see what
is not yet implemented, and avoiding a catch-all wildcard arm is less
error-prone as opcodes are added in the future.

However, the x64 backend was the exception: as @akirilov-arm pointed
out, it had a wildcard match arm. This fixes the issue by explicitly
listing all opcodes the x64 backend does not yet implement.

As per our tests, these opcodes are not used or need by Wasm lowering;
but, it is good to know that they exist, so that we can eventually
either support or remove them.

This was a good exercise for me as I wasn't aware of a few of these in
particular: e.g., aarch64 supports `bmask` while x64 does not, and there
isn't a good reason why x64 shouldn't, especially if others hope to use
Cranelift as a SIMD-capable general codegen in the future.

The `unimplemented!()` cases are separate from `panic!()` ones: my
convention here was to split out those that are logically just *missing*
from those that should be *impossible*, mostly due to expected removal
by legalization before we reach the lowering step.
2021-06-26 15:29:14 -07:00
Afonso Bordado
e85eb77c45 aarch64: Implement missing atomic rmw ops 2021-06-25 07:51:46 +01:00
Chris Fallin
652f21e3e0 Merge pull request #3026 from afonso360/aarch64-elf-tls
aarch64: Implement TLS ELF GD Relocations
2021-06-24 11:54:34 -07:00
Chris Fallin
7d47ba12c5 Merge pull request #3028 from cfallin/x86-legacy
cranelift-codegen: move old x86 and RISC-V backends to isa/legacy/.
2021-06-24 11:38:08 -07:00
Chris Fallin
4b2723abb0 cranelift-codegen: move old x86 and RISC-V backends to isa/legacy/.
These backends will be removed in the future (see
bytecodealliance/rfcs#12 and the pending #3009 in this repo).

In the meantime, to more clearly communicate that they are using
"legacy" APIs and will eventually be removed, this PR places them in an
`isa/legacy/` subdirectory. No functional changes otherwise.
2021-06-24 11:03:47 -07:00