Commit Graph

7815 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
e3ff551c2b Add Intel BMI1 ctz and clz encodings. 2017-07-14 14:01:02 -07:00
Jakob Stoklund Olesen
f91d747bda Add support for setting presets.
Fixes #11.

Presets are groups of settings and values applied at once. This is used
as a shorthand in test files, so for example "isa intel nehalem" enables
all of the CPUID bits that the Nehalem micro-architecture provides.
2017-07-14 13:57:44 -07:00
Jakob Stoklund Olesen
4bb0e2014c Add support for setting presets.
Fixes #11.

Presets are groups of settings and values applied at once. This is used
as a shorthand in test files, so for example "isa intel nehalem" enables
all of the CPUID bits that the Nehalem micro-architecture provides.
2017-07-14 13:57:44 -07:00
Dan Gohman
130b7fa2fa Add documentation for immediates with type bool.
This makes the documentation for the new bconst instruction more complete.
2017-07-13 16:23:41 -07:00
Dan Gohman
89634fa645 Add documentation for immediates with type bool.
This makes the documentation for the new bconst instruction more complete.
2017-07-13 16:23:41 -07:00
Jakob Stoklund Olesen
6d6035b918 CSSA verifier.
During register allocation, the code must be kept in conventional SSA
form. Add a verifier that checks this property.
2017-07-13 13:18:18 -07:00
Jakob Stoklund Olesen
52dae7c2e2 CSSA verifier.
During register allocation, the code must be kept in conventional SSA
form. Add a verifier that checks this property.
2017-07-13 13:18:18 -07:00
Dan Gohman
5a4aa11274 Add a bconst instruction. (#116)
* Add a bconst instruction.
2017-07-13 10:12:25 -07:00
Dan Gohman
3bcfb103b9 Add a bconst instruction. (#116)
* Add a bconst instruction.
2017-07-13 10:12:25 -07:00
Jakob Stoklund Olesen
5cbcd59cf0 Add some ISA predicates for Intel CPUID features.
Guard the popcnt instruction on the proper CPUID bits.
2017-07-12 16:05:20 -07:00
Jakob Stoklund Olesen
d8e2cb2b42 Add some ISA predicates for Intel CPUID features.
Guard the popcnt instruction on the proper CPUID bits.
2017-07-12 16:05:20 -07:00
Jakob Stoklund Olesen
435a15b88d Add Intel encodings for popcnt.
Change the result type for the bit-counting instructions from a fixed i8
to the iB type variable which is the type of the input. This matches the
convention in WebAssembly, and at least Intel's instructions will set a
full register's worth of count result, even if it is always < 64.

Duplicate the Intel 'ur' encoding recipe into 'umr' and 'urm' variants
corresponding to the RM and MR encoding variants. The difference is
which register is encoded as 'reg' and which is 'r/m' in the ModR/M
byte. A 'mov' register copy uses the MR variant, a unary popcnt uses the
RM variant.
2017-07-12 14:17:16 -07:00
Jakob Stoklund Olesen
b6f2f0d862 Add Intel encodings for popcnt.
Change the result type for the bit-counting instructions from a fixed i8
to the iB type variable which is the type of the input. This matches the
convention in WebAssembly, and at least Intel's instructions will set a
full register's worth of count result, even if it is always < 64.

Duplicate the Intel 'ur' encoding recipe into 'umr' and 'urm' variants
corresponding to the RM and MR encoding variants. The difference is
which register is encoded as 'reg' and which is 'r/m' in the ModR/M
byte. A 'mov' register copy uses the MR variant, a unary popcnt uses the
RM variant.
2017-07-12 14:17:16 -07:00
Jakob Stoklund Olesen
f57c666d8a Add Intel encodings for shift and rotate instructions. 2017-07-12 13:12:24 -07:00
Jakob Stoklund Olesen
5615e4a9e7 Add Intel encodings for shift and rotate instructions. 2017-07-12 13:12:24 -07:00
Jakob Stoklund Olesen
1f52415b17 Add a WebAssembly filetests directory.
Start adding little 'test compile' test cases which check that the full
compilation pipeline works for each WebAssembly instruction.
2017-07-12 12:22:50 -07:00
Jakob Stoklund Olesen
3d738d01bb Add a WebAssembly filetests directory.
Start adding little 'test compile' test cases which check that the full
compilation pipeline works for each WebAssembly instruction.
2017-07-12 12:22:50 -07:00
Jakob Stoklund Olesen
9e3b6a6eba Add a Context::compile() function which runs all compiler passes.
This is the main entry point to the code generator. It returns the
computed size of the functions code.

Also add a 'test compile' command which runs the whole code generation
pipeline.
2017-07-12 12:22:49 -07:00
Jakob Stoklund Olesen
6cc729a69b Add a Context::compile() function which runs all compiler passes.
This is the main entry point to the code generator. It returns the
computed size of the functions code.

Also add a 'test compile' command which runs the whole code generation
pipeline.
2017-07-12 12:22:49 -07:00
Jakob Stoklund Olesen
ae5e440094 Fix Vim syntax highlighting of numbers.
Cretonne allows '_' in number constants.
2017-07-12 12:22:49 -07:00
Jakob Stoklund Olesen
07a96e609e Fix Vim syntax highlighting of numbers.
Cretonne allows '_' in number constants.
2017-07-12 12:22:49 -07:00
Jakob Stoklund Olesen
d56d4d171e Tag the regmove instruction with other_side_effects.
This instruction moves a value between registers. This counts as a side
effect that is not tracked by the SSA data flow graph.
2017-07-12 10:43:42 -07:00
Jakob Stoklund Olesen
6e0834eea9 Tag the regmove instruction with other_side_effects.
This instruction moves a value between registers. This counts as a side
effect that is not tracked by the SSA data flow graph.
2017-07-12 10:43:42 -07:00
Jakob Stoklund Olesen
0917cfe7f4 Attach encodings to regmove instructions generated during coloring.
All emitted regmove instructions must be materialized as real move
instructions.
2017-07-12 10:43:42 -07:00
Jakob Stoklund Olesen
abc1743486 Attach encodings to regmove instructions generated during coloring.
All emitted regmove instructions must be materialized as real move
instructions.
2017-07-12 10:43:42 -07:00
Jakob Stoklund Olesen
ca99bd1641 Add RISC-V regmove encodings. 2017-07-12 10:43:42 -07:00
Jakob Stoklund Olesen
2ee37784ff Add RISC-V regmove encodings. 2017-07-12 10:43:42 -07:00
Jakob Stoklund Olesen
ad76f80127 Add Intel regmove encodings.
Same as a register copy, but different arguments.
2017-07-12 10:43:42 -07:00
Jakob Stoklund Olesen
edffd848bf Add Intel regmove encodings.
Same as a register copy, but different arguments.
2017-07-12 10:43:42 -07:00
Jakob Stoklund Olesen
69f974ba5d Add an ISA argument to dfg.display_inst().
Include ISA-specific annotations in tracing and error messages.
2017-07-12 10:13:13 -07:00
Jakob Stoklund Olesen
b6d4b884ad Add an ISA argument to dfg.display_inst().
Include ISA-specific annotations in tracing and error messages.
2017-07-12 10:13:13 -07:00
Jakob Stoklund Olesen
e4da2e1f22 Include ISA-specific information in verifier errors.
When the test driver reports a verifier error, make sure to include the
TargetIsa when printing the failing function.
2017-07-12 10:13:13 -07:00
Jakob Stoklund Olesen
71af555e6f Include ISA-specific information in verifier errors.
When the test driver reports a verifier error, make sure to include the
TargetIsa when printing the failing function.
2017-07-12 10:13:13 -07:00
Jakob Stoklund Olesen
924c4649cc Enforce encodings for instructions with side effects.
We allow ghost instructions to exist if they have no side effects.
Instructions that affect control flow or that have other side effects
must be encoded.

Teach the IL verifier to enforce this. Once any instruction has an
encoding, all instructions with side effects must have an encoding.
2017-07-12 09:41:25 -07:00
Jakob Stoklund Olesen
24b53efc9d Enforce encodings for instructions with side effects.
We allow ghost instructions to exist if they have no side effects.
Instructions that affect control flow or that have other side effects
must be encoded.

Teach the IL verifier to enforce this. Once any instruction has an
encoding, all instructions with side effects must have an encoding.
2017-07-12 09:41:25 -07:00
Jakob Stoklund Olesen
fc94ce7e8c Add an other_side_effects instruction flag.
This is used to indicate instructions that have some side effect that is
not modelled by the more specific instruction flags.
2017-07-12 09:15:40 -07:00
Jakob Stoklund Olesen
6ee432329d Add an other_side_effects instruction flag.
This is used to indicate instructions that have some side effect that is
not modelled by the more specific instruction flags.
2017-07-12 09:15:40 -07:00
d1m0
7c438f866c Add fix for #114 (#115)
* Reduce code duplication in TypeConstraint subclasses; Add ConstrainWiderOrEqual to ti and to ireduce,{s,u}extend and f{promote,demote}; Fix bug in emitting constraint edges in TypeEnv.dot(); Modify runtime constraint checks to reject match when they encounter overflow

* Rename Constrain types to something shorter; Move lane_bits/lane_counts in subclasses of ValueType; Add wider_or_eq function in rust and python;
2017-07-12 08:51:55 -07:00
d1m0
a9147ebd30 Add fix for #114 (#115)
* Reduce code duplication in TypeConstraint subclasses; Add ConstrainWiderOrEqual to ti and to ireduce,{s,u}extend and f{promote,demote}; Fix bug in emitting constraint edges in TypeEnv.dot(); Modify runtime constraint checks to reject match when they encounter overflow

* Rename Constrain types to something shorter; Move lane_bits/lane_counts in subclasses of ValueType; Add wider_or_eq function in rust and python;
2017-07-12 08:51:55 -07:00
Denis Merigoux
962c945a3c Cretonne IL frontend: ILBuilder (#97)
* API and data structures proposal for the SSA construction module

* Polished API and implemented trivial functions

* API more explicit, Variable now struct parameter

* Sample test written to see how the API could be used

* Implemented local value numbering for SSABuilder

* Implemented SSA within a single Ebb

* Unfinished unoptimized implementation for recursive use and seal

* Working global value numbering
The SSABuilder now create ebb args and modifies jump instructions accordingly

* Updated doc and improved branch argument modifying.
Removed instructions::branch_arguments and instructions::branch_argument_mut

* SSA building: bugfix, asserts and new test case
Missing a key optimization to remove cycles of Phi

* SSA Building: small changes after code review
Created helper function for seal_block (which now contains sanity checks)

* Optimization: removed useless phis (ebb arguments)
Using pessimistic assumption that when using a non-def variable in an unsealed block we create an ebb argument which is removed when sealing if we detect it as useless
Using aliases to avoid rewriting variables

* Changed the semantics of remove_ebb_arg and turned it into a proper API method

* Adapted ssa branch to changes in the DFG API

* Abandonned SparseMaps for EntityMaps, added named structure for headr block data.

* Created skeletton for a Cretonne IL builder frontend

* Frontend IL builder: first draft of implementation with example of instruction methods

* Working basic implementation of the frontend
Missing handling of function arguments and return values

* Interaction with function signature, sample test, more checks

* Test with function verifier, seal and fill sanity check

* Implemented python script to generate ILBuilder methods

* Added support for jump tables and stack slot

* Major API overhaul
* No longer generating rust through Python but implements InstBuilder
* No longer parametrized by user's blocks but use regular `Ebb`
* Reuse of allocated memory via distinction between ILBuilder and FunctionBuilder

* Integrate changes from StackSlot

* Improved error message

* Added support for jump arguments supplied by the user

* Added an ebb_args proxy method needed

* Adapted to Entity_ref splitted into a new module

* Better error messages and fixed tests

* Added method to change jump destination

* We whould be able to add unreachable code

* Added inst_result proxy to frontend

* Import support

* Added optimization for SSA construction:
If multiple predecessors but agree on value don't create EBB argument

* Move unsafe and not write-only funcs apart, improved doc

* Added proxy function for append_ebb_arg

* Support for unreachable code and better layout of the Ebbs

* Fixed a bug yielding an infinite loop in SSA construction

* SSA predecessors lookup code refactoring

* Fixed bug in unreachable definition

* New sanity check and display debug function

* Fixed bug in verifier and added is_pristine ;ethod for frontend

* Extended set of characters printable in function names
To be able to print names of functions in test suite

* Fixes and improvements of SSA construction after code review

* Bugfixes for frontend code simplification

* On-the-fly critical edge splitting in case of br_table with jump arguments

* No more dangling undefined values, now attached as EBB args

* Bugfix: only split corresponding edges on demand, not all br_table edges

* Added signature retrieval method

* Bugfix for critical edge splitting not sealing the ebbs it created

* Proper handling of SSA side effects by the frontend

* Code refactoring: moving frontend and SSA to new crate

* Frontend: small changes and bugfixes after code review
2017-07-11 15:08:57 -07:00
Denis Merigoux
de5501bc47 Cretonne IL frontend: ILBuilder (#97)
* API and data structures proposal for the SSA construction module

* Polished API and implemented trivial functions

* API more explicit, Variable now struct parameter

* Sample test written to see how the API could be used

* Implemented local value numbering for SSABuilder

* Implemented SSA within a single Ebb

* Unfinished unoptimized implementation for recursive use and seal

* Working global value numbering
The SSABuilder now create ebb args and modifies jump instructions accordingly

* Updated doc and improved branch argument modifying.
Removed instructions::branch_arguments and instructions::branch_argument_mut

* SSA building: bugfix, asserts and new test case
Missing a key optimization to remove cycles of Phi

* SSA Building: small changes after code review
Created helper function for seal_block (which now contains sanity checks)

* Optimization: removed useless phis (ebb arguments)
Using pessimistic assumption that when using a non-def variable in an unsealed block we create an ebb argument which is removed when sealing if we detect it as useless
Using aliases to avoid rewriting variables

* Changed the semantics of remove_ebb_arg and turned it into a proper API method

* Adapted ssa branch to changes in the DFG API

* Abandonned SparseMaps for EntityMaps, added named structure for headr block data.

* Created skeletton for a Cretonne IL builder frontend

* Frontend IL builder: first draft of implementation with example of instruction methods

* Working basic implementation of the frontend
Missing handling of function arguments and return values

* Interaction with function signature, sample test, more checks

* Test with function verifier, seal and fill sanity check

* Implemented python script to generate ILBuilder methods

* Added support for jump tables and stack slot

* Major API overhaul
* No longer generating rust through Python but implements InstBuilder
* No longer parametrized by user's blocks but use regular `Ebb`
* Reuse of allocated memory via distinction between ILBuilder and FunctionBuilder

* Integrate changes from StackSlot

* Improved error message

* Added support for jump arguments supplied by the user

* Added an ebb_args proxy method needed

* Adapted to Entity_ref splitted into a new module

* Better error messages and fixed tests

* Added method to change jump destination

* We whould be able to add unreachable code

* Added inst_result proxy to frontend

* Import support

* Added optimization for SSA construction:
If multiple predecessors but agree on value don't create EBB argument

* Move unsafe and not write-only funcs apart, improved doc

* Added proxy function for append_ebb_arg

* Support for unreachable code and better layout of the Ebbs

* Fixed a bug yielding an infinite loop in SSA construction

* SSA predecessors lookup code refactoring

* Fixed bug in unreachable definition

* New sanity check and display debug function

* Fixed bug in verifier and added is_pristine ;ethod for frontend

* Extended set of characters printable in function names
To be able to print names of functions in test suite

* Fixes and improvements of SSA construction after code review

* Bugfixes for frontend code simplification

* On-the-fly critical edge splitting in case of br_table with jump arguments

* No more dangling undefined values, now attached as EBB args

* Bugfix: only split corresponding edges on demand, not all br_table edges

* Added signature retrieval method

* Bugfix for critical edge splitting not sealing the ebbs it created

* Proper handling of SSA side effects by the frontend

* Code refactoring: moving frontend and SSA to new crate

* Frontend: small changes and bugfixes after code review
2017-07-11 15:08:57 -07:00
Jakob Stoklund Olesen
a4a8c83aab Start adding Intel 64-bit encodings.
Add a TailRecipe.rex() method which creates an encoding recipe with a
REX prefix.

Define I64 encodings with REX.W for i64 operations and with/without REX
for i32 ops. Only test the with-REX encodings for now. We don't yet have
an instruction shrinking pass that can select the non-REX encodings.
2017-07-11 11:05:27 -07:00
Jakob Stoklund Olesen
6ae4eb82f8 Start adding Intel 64-bit encodings.
Add a TailRecipe.rex() method which creates an encoding recipe with a
REX prefix.

Define I64 encodings with REX.W for i64 operations and with/without REX
for i32 ops. Only test the with-REX encodings for now. We don't yet have
an instruction shrinking pass that can select the non-REX encodings.
2017-07-11 11:05:27 -07:00
Jakob Stoklund Olesen
fb227cb389 Move Intel recipe_* bodies into intel/recipes.py.
Use a PUT_OP macro in the TailRecipe Python class to replace the code
snippet that emits the prefixes + opcode part of the instruction encoding.

Prepare for the addition of REX prefixes by giving the PUT_OP functions
a third argument representing the REX prefix. For the non-REX encodings,
verify that no REX bits wold be needed.
2017-07-11 11:05:27 -07:00
Jakob Stoklund Olesen
263779ac56 Move Intel recipe_* bodies into intel/recipes.py.
Use a PUT_OP macro in the TailRecipe Python class to replace the code
snippet that emits the prefixes + opcode part of the instruction encoding.

Prepare for the addition of REX prefixes by giving the PUT_OP functions
a third argument representing the REX prefix. For the non-REX encodings,
verify that no REX bits wold be needed.
2017-07-11 11:05:27 -07:00
d1m0
f837dcf4b7 Handle bound instructions in pattern type inference (#113) 2017-07-11 08:39:22 -07:00
d1m0
c5cddc3eac Handle bound instructions in pattern type inference (#113) 2017-07-11 08:39:22 -07:00
d1m0
fc11ae7b72 Emit runtime type checks in legalizer.rs (#112)
* Emit runtime type checks in legalizer.rs
2017-07-10 15:28:32 -07:00
d1m0
98f822f347 Emit runtime type checks in legalizer.rs (#112)
* Emit runtime type checks in legalizer.rs
2017-07-10 15:28:32 -07:00
Jakob Stoklund Olesen
528e6ff3f5 Generate instruction unwrapping code for binemit recipes.
Generate code to:

- Unwrap the instruction and generate an error if the instruction format
  doesn't match the recipe.
- Look up the value locations of register and stack arguments.

The recipe_* functions in the ISA binemit modules now take these
unwrapped items as arguments.

Also add an optional `emit` argument to the EncRecipe constructor which
makes it possible to provide inline Rust code snippets for code
emission. This requires a lot less boilerplate than recipe_* functions.
2017-07-07 15:10:17 -07:00