Add new instruction predicates to support the 'I' encoding recipe: IsSignedInt,
IsUnsignedInt used to test that an immediate operand is in the allowed range.
Each InstructionFormat instance gets data members corresponding to its immediate
operands, so the can be referred to as BinaryImm.imm, for example.
This will be used to construct instruction predicates.
Usually an instruction firmat has only a single immediate operand called 'imm',
or 'cond' if it is one of the condigtion codes. Add a 'default_member' field to
ImmediateKind to keep track of this default member name in the InstructionData
struct.
We have multiple pre-computed constant hash tables that all use the same
quadratic probing algorithm.
Add a constant_hash Rust module to match the meta/constant_hash.py module.
Move the simple_hash() function into constant_hash. Its Python equivalent is in
the constant_hash.py module.
The integration tests use both libcretonne and libreader, so moving them avoids
the circular dev-dependency.
Also go back to building everything under src/tools/target to avoid rebuilding
the libraries when cargo is invoked in different subdirectories. This speeds up
test-all.sh quite a bit.
Finally, skip the pure debug build. We build "cargo test" and "cargo build
--release" which should cover everything we need.
Predcates are boolean functions. There will be ISA predicates and instruction
predicates.
The ISA predicates will be turned into member functions on the generated Flags
structs.
Add an isa::lookup() function which serves as a target registry for creating
Box<TargetIsa> trait objects.
An isa::Builder makes it possible to confugure the trait object before it is
created.
- Move detail data structures into a settings::detail module to avoid polluting
the settings namespace.
- Rename generated data types to 'Flags' in anticipation of computed predicate
flags that can't be set. The Flags struct is immutable.
- Use a settings::Builder struct to manipulate settings, then pass it to
Flags::new().
This trait allows settings to be manipulated as strings, using descriptors and
constant hash-table lookups.
Amend gen_settings.py to generate the necessary constant tables.
Clarify terminology by always referring to a 'Target ISA' instead of just
'Target'. Use 'isa' as a module name instead of 'target' both in Rust and Python
code.
This is only to clarify terminology and not at all because Cargo insists on
using the 'target' sub-directory for build products. Oh, no. Not at all.
The shift instructions have two type variables since the shift amount can be a
differently sized integer. Fix the RISC-V shift encodings to reflect this, and
allow i64 registers to be shifted by an i32 amount.
Move the CPUMode reference from EncRecipe to the Encoding itself, allowing
EncRecipes to be shared between CPU modes. At least RISC-V should be able to
share some recipes between RV32 and RV64 modes.
Require this trait on the value type stored in an EntityMap to 'unlock' the
methods intended for primary entity maps that are allowed to create references
with the 'push method.
This prevents accidentally depending on these methods in secondary maps.
This iterator enumerates all EBB references whether they are in the layout or
not. That is usually not what is needed when working with the CFG.
It is better to iterate over EBB referrences in layout order, or in reverse
post-order and then call the get_predecessors() method for each Ebb reference.
See the new implementation of print_cfg::cfg_connections().
