Commit Graph

510 Commits

Author SHA1 Message Date
Nicolas B. Pierron
592f5445dd Fix legalize-br-table test case for basic blocks. (#990) 2019-09-06 14:26:17 -06:00
Benjamin Bouvier
dca2e7e9a7 Add basic test for the pinned register; 2019-09-06 16:18:27 +02:00
Dan Gohman
d858ebb4aa Bump version to 0.42.0 2019-09-05 17:36:04 -07:00
Ujjwal Sharma
dce8ad8229 [codegen] add encodings for isub borrow variants
Add encodings for isub borrow variants (isub_bout, isub_bin,
isub_borrow) for x86_32, enabling the legalization for isub.i64 to work.

Bug: https://bugzilla.mozilla.org/show_bug.cgi?id=1576675
Bug: https://github.com/CraneStation/cranelift/issues/765
2019-09-05 19:28:33 +02:00
Ujjwal Sharma
ea919489ee [codegen] add encodings for iadd carry variants (#961)
* [codegen] add encodings for iadd carry variants

Add encodings for iadd carry variants (iadd_cout, iadd_cin, iadd_carry)
for x86_32, enabling the legalization for iadd.i64 to work.

* [codegen] remove support for iadd carry variants on riscv

Previously, the carry variants of iadd (iadd_cin, iadd_cout and
iadd_carry) were being legalized for isa/riscv since RISC architectures
lack a flags register.

This forced us to return and accept booleans for these operations, which
proved to be problematic and inconvenient, especially for x86.

This commit removes support for said statements and all dependent
statements for isa/riscv so that we can work on a better legalization
strategy in the future.

* [codegen] change operand type from bool to iflag for iadd carry variants

The type of the carry operands for the carry variants of the iadd
instruction (iadd_cin, iadd_cout, iadd_carry) was bool for compatibility
reasons for isa/riscv. Since support for these instructions on RISC
architectures has been temporarily suspended, we can safely change the
type to iflags.
2019-09-05 15:03:13 +02:00
Nicolas B. Pierron
7e398af999 Basic-block: Insert regmove instructions in new blocks dedicated to hold the diversions. 2019-09-05 14:55:35 +02:00
Benjamin Bouvier
49a37e48fb [codegen] Make scalar_to_vector's output type a lane of its input type; 2019-09-04 19:09:54 +02:00
Andrew Brown
d64e454004 Improve uimm128 parsing
This commit changes 128-bit constant parsing in two ways:
 - it adds the ability to use underscores to separate digits when writing a 128-bit constant in hexadecimal; e.g. `0x00010203...` can now be written as `0x0001_0203_...`
 - it adds a new mechanism for parsing 128-bit constants using integer/float/boolean literals; e.g. `vconst.i32x4 [1 2 3 4]`. Note that currently the controlling type of the instruction dictates how many literals to parse inside the brackets.
2019-09-04 07:16:04 -07:00
Julian Seward
98056aa05d Don't incorrectly omit a REX prefix for some encodings of copy_to_ssa. Mozilla bug #1576969.
Also, as a ridealong fix, removes R32 encodings for x86_64 in `enc_r32_r64`,
since the type `rXX` by definition only exists for targets with word size `XX`
bits.
2019-09-04 13:59:01 +02:00
Dan Gohman
8becc9a64c Bump version to 0.41.0 2019-08-30 23:22:48 -07:00
Nicolas B. Pierron
381578311c Split edges to have a block to add regmove & copy instructions.
When using basic block instructions cannot be added in-between jump instructions which are ending basic blocks. These changes create extra basic blocks such that extra space is available for the spilling and moving registers where they are expected.
2019-08-30 18:44:35 +02:00
Nicolas B. Pierron
04b10b3fde Add feature flags to test files.
Cranelift can be compiled with feature flags which can change its output. To
accomodate changes of output related to feature flags, test file can now include
`feature "..."` and `feature ! "..."` directives in the preamble of the test
file.

The test runner would skip the test if the flag does not match the expectation
of the test case.
2019-08-28 16:42:07 +02:00
Andrew Brown
9612c71fbd Remove calling convention on FunctionRunner test
For this test to run on Windows, the explicit calling convention
must be removed so that the parser is free to use the host's
calling convention.
2019-08-28 16:33:25 +02:00
Andrew Brown
6fdc69ff2e Add options for parsing test files (#942)
* Add options for parsing test files

This change allows adding parsing parameters more easily; e.g. a parameter is needed for setting the default calling convention for functions parsed as a part of the `run` test feature.

* Set default calling convention that of the host for `test run` file tests

Previously `test run` used the parser's hard-coded CallConv::Fast as the default calling convention but with this change any test being `run` will use the default calling convention of the machine running the test. `test run` will now throw an error if the calling convention of the function does not match the host's.
2019-08-27 20:31:08 +02:00
Andrew Brown
020e5987d3 Use little-endian ordering for CLIF vconst immediate
Examining wasm-objdump revealed that it stores SIMD constants in little-endian order, e.g.:

000071 func[2] <test_const>:
 000072: fd 02 01 00 00 00 02 00 00 | v128.const 0x00000001 0x00000002 0x00000003 0x00000004
 00007b: 00 03 00 00 00 04 00 00 00 |
 000084: fd 0d 03                   | i32x4.extract_lane 3
 000087: 0b                         | end

This change avoids confusion by making the CLIF representation use little-endian order as well.
2019-08-26 16:12:06 -07:00
Andrew Brown
c3cc225de9 Add filetest for verifying emitted rodata (i.e. test rodata) 2019-08-26 16:12:06 -07:00
Andrew Brown
8d812b24cc Add x86 encoding for vconst 2019-08-26 16:12:06 -07:00
Andrew Brown
7b2d055f78 Add ability to relocate constants using RelocSink 2019-08-26 16:12:06 -07:00
Till Schneidereit
9edbfed65f Switch from mmap to memmap to support Windows 2019-08-26 14:07:39 +02:00
Ujjwal Sharma
ec8f72bf20 Use roundss/roundsd when available for Ceil/Floor/Trunc/Nearest (#931)
Don't tie the preexisting SIMD ISA predicates to the shared
enable_simd setting but make new ones instead.

Fixes: https://github.com/CraneStation/cranelift/issues/908
2019-08-26 13:37:27 +02:00
julian-seward1
b8fb52446c Cranelift: implement redundant fill removal on tree-shaped CFG regions. Mozilla bug 1570584. (#906) 2019-08-25 19:37:34 +02:00
Andrew Brown
cc57e84cbd Fix segfault due to b64 encoding (#919)
* Fix segfault due to b64 encoding

Prior to this patch, bconst.b64 encoded its instruction with a 32-bit immediate that caused improper decoding of the MOV instruction; instead, use a REX prefix and rely on zero-extension of the immediate. Fixes #911.
2019-08-23 18:04:34 +02:00
Andrew Brown
ff3c44385c Add test run to cranelift-filetests to allow executing CLIF (#890)
* Add ability to run CLIF IR using `clif-util run [-v] {file}` and add `test run` to cranelift-filetests to allow executing CLIF

This re-factors the compile/execute parts to a FunctionRunner that is shared between cranelift-filetests and clif-util. CLIF can be now be run using `clif-util run` as well as during `clif-util test` for files with a `test run` header. As before, only functions suffixed with a `run` comment are executed. The `run: fn(...) == ...` expression syntax is left for a subsequent change.
2019-08-21 18:03:09 +02:00
Dan Gohman
13f83d8291 Bump version to 0.40.0 2019-08-20 15:32:19 -07:00
Dan Gohman
fbfeaaa32b Revert the test changes too.
In 1169dc520815fa4a6b1285914748408729a28caa, I forgot to git add the
test file changes.
2019-08-20 15:26:52 -07:00
Dan Gohman
0d54517d35 Bump version to 0.39.0 2019-08-20 14:26:16 -07:00
Dan Gohman
0c2c597852 Update to latest versions of term, capstone, wabt, goblin, wasmparser. 2019-08-20 14:18:14 -07:00
Andrew Brown
b4ef90cfcd Remove SSE2 setting for x86
In talking to @sunfishcode, he preferred to avoid the confusion of more ISA predicates by eliminating SSE2. SSE2 was released with the Pentium 4 in 2000 so it is unlikely that current CPUs would have SIMD enabled and not have this feature. I tried to note the SSE2-specific instructions with comments in the code.
2019-08-20 10:21:12 -07:00
Andrew Brown
3fdc78174f Add x86 implementation of extractlane instruction 2019-08-20 10:21:12 -07:00
Carmen Kwan
19257f80c1 Add reference types R32 and R64
-Add resumable_trap, safepoint, isnull, and null instructions
-Add Stackmap struct and StackmapSink trait

Co-authored-by: Mir Ahmed <mirahmed753@gmail.com>
Co-authored-by: Dan Gohman <sunfish@mozilla.com>
2019-08-16 11:35:16 -07:00
Benjamin Bouvier
b659262d2a Use aliasing instead of copying in simple_preopt; 2019-08-16 10:41:51 -07:00
Benjamin Bouvier
2ee35b7ea1 Implement a Windows Baldrdash calling convention; 2019-08-16 14:25:15 +02:00
Sean Stangl
c7b4b98cac Add a fold_redundant_jumps() pass to the branch relaxation phase. (#887) 2019-08-09 15:30:11 -06:00
Yury Delendik
00b8d019c9 Bump version to 0.38.0 (#894) 2019-08-06 14:41:13 -05:00
Benjamin Bouvier
627ba24b59 Simplify jump table instructions and add missing conversion;
This makes non-legalized jump table instructions operate on operands with
pointer-sized types. This means we need to extend smaller types into the
pointer-sized operand, when the two don't match.
2019-08-02 18:39:39 +02:00
Nicolas B. Pierron
f0d7438728 Properly legalize with empty jump tables. 2019-08-01 13:47:28 +02:00
iximeow
6e57e3f8f3 preopt: use replaced arg after having replaced BinaryImm
when replacing BinaryImm, we use the prior arg, but later use the arg
that was replaced when writing an alias if we can determine the new op
is actually equivalent to a simple copy
2019-08-01 11:00:37 +02:00
Benjamin Bouvier
23ac723d4c Simple preopt: fold instructions using simple algebraic identities; 2019-07-31 17:42:05 +02:00
Benjamin Bouvier
2fef2eef67 Simple preopt: try to fold right-shift of left-shift into an extended move; 2019-07-31 17:42:05 +02:00
bjorn3
8e33ca3055 Fix tests 2019-07-31 15:20:08 +02:00
Dan Gohman
16e16c49a7 Bump version to 0.37.0 2019-07-27 04:50:19 -07:00
Nicolas B. Pierron
42ebd2a5f4 Fix licm/jump-table-entry.clif test case to work with basic blocks. 2019-07-25 14:28:07 +02:00
Dan Gohman
4641fdd302 Bump version to 0.36.0 2019-07-19 16:28:40 -07:00
Andrew Brown
084e279def Add x86 implementation of splat instruction 2019-07-16 17:07:44 -07:00
Andrew Brown
3b36a1d1d8 Add x86 implementation of insertlane instruction 2019-07-16 17:07:44 -07:00
Andrew Brown
683e7c75a3 Add x86-specific shuffle instructions
This includes both PSHUFD and PSHUFB; these are necessary to legalize future SIMD instructions.
2019-07-16 17:07:44 -07:00
Andrew Brown
61772e9775 Add raw_bitcast instruction
Casts bits as a different type of the same width with no change to the data (unlike bitcast)
2019-07-16 17:07:44 -07:00
Andrew Brown
5f0e5567c1 Add scalar_to_vector instruction
Moves scalar values in a GPR register to an FPR register
2019-07-16 17:07:44 -07:00
Andrew Brown
f2c48009e8 Disable SIMD features by default 2019-07-16 17:07:44 -07:00
Dan Gohman
67dd0b5015 Bump version to 0.35.0 2019-07-12 15:48:19 -07:00