Commit Graph

6 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
1d21422032 Generate register class descriptors.
Add a mechanism for defining sub-classes of register classes.
2017-01-20 14:23:06 -08:00
Jakob Stoklund Olesen
fb4db38dd6 Fill in boilerplate for Intel and ARM targets.
The intel, arm32, and arm32 targets were only defined in the meta
language previously. Add Rust implementations too.

This is mostly boilerplate, except for the unit tests in the
registers.rs files.
2016-11-23 10:42:07 -08:00
Jakob Stoklund Olesen
353caf23cd Generate register bank descriptions.
Use the information in the ISA's registers.py files to generate a
RegInfo Rust data structure.
2016-11-22 18:15:21 -08:00
Jakob Stoklund Olesen
060735adfe Define register classes for 4 ISAs. 2016-11-11 15:08:12 -08:00
Jakob Stoklund Olesen
e1c0171b2c Define register banks.
Add a RegBank class for describing CPU register banks.

Define register banks for all the ISA stubs. The ARM32 floating point
bank in particular requires attention.
2016-11-11 14:17:10 -08:00
Jakob Stoklund Olesen
34f7b93482 Add stubs for Intel and ARM architectures.
The Intel ISA handles both 32-bit and 64-bit code.

ARM is split into separate arm32 and arm64 ISAs since the architectures
have little in common in instruction encodings and register files.
2016-11-11 11:32:05 -08:00