Commit Graph

17 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
c01ff670ed Fixed for mypy 0.501.
The List and Dict types are no longer implicitly available. They must be
imported from typing.

Type annotations must appear before the doc comment in a function. Also
fix type errors in these functions that weren't detected before.
2017-03-03 09:08:28 -08:00
Jakob Stoklund Olesen
aa7e349134 Add a section about implementation limits.
Fix a few other minor issues with the documentation.
2017-02-24 11:08:15 -08:00
Jakob Stoklund Olesen
377550b835 Add return_reg encodings for RISC-V. 2017-02-21 16:29:23 -08:00
Jakob Stoklund Olesen
2390e3e3f0 Add operand register constraints.
Every encoding recipe must specify register constraints on input and
output values.

Generate recipe constraint tables along with the other encoding tables.
2017-01-25 13:35:18 -08:00
Jakob Stoklund Olesen
1d21422032 Generate register class descriptors.
Add a mechanism for defining sub-classes of register classes.
2017-01-20 14:23:06 -08:00
Jakob Stoklund Olesen
fb4db38dd6 Fill in boilerplate for Intel and ARM targets.
The intel, arm32, and arm32 targets were only defined in the meta
language previously. Add Rust implementations too.

This is mostly boilerplate, except for the unit tests in the
registers.rs files.
2016-11-23 10:42:07 -08:00
Jakob Stoklund Olesen
353caf23cd Generate register bank descriptions.
Use the information in the ISA's registers.py files to generate a
RegInfo Rust data structure.
2016-11-22 18:15:21 -08:00
Jakob Stoklund Olesen
060735adfe Define register classes for 4 ISAs. 2016-11-11 15:08:12 -08:00
Jakob Stoklund Olesen
e1c0171b2c Define register banks.
Add a RegBank class for describing CPU register banks.

Define register banks for all the ISA stubs. The ARM32 floating point
bank in particular requires attention.
2016-11-11 14:17:10 -08:00
Jakob Stoklund Olesen
34f7b93482 Add stubs for Intel and ARM architectures.
The Intel ISA handles both 32-bit and 64-bit code.

ARM is split into separate arm32 and arm64 ISAs since the architectures
have little in common in instruction encodings and register files.
2016-11-11 11:32:05 -08:00
Jakob Stoklund Olesen
581294dafe Use uppercase for the global riscv.ISA constant. 2016-11-11 11:17:40 -08:00
Jakob Stoklund Olesen
8846cb8105 Move ISA definitions into cdsl.isa.
The cretonne package is now split into two: cdsl and base.
2016-11-08 13:21:05 -08:00
Jakob Stoklund Olesen
0b9b956695 Split out instruction definitions.
- cdsl.instructions defines the Instruction class.
- base.instructions defines the base instruction set.
2016-11-08 12:33:50 -08:00
Jakob Stoklund Olesen
eb688dc72d Move formats, entities, and immediates to the base package.
- base.formats defines instruction formats.
- base.entities defines kinds of entity references.
- base.immediates defines kinds of imediate operands.
2016-11-08 11:06:37 -08:00
Jakob Stoklund Olesen
e6b959436d Split out predicates and settings.
- cdsl.predicates defines classes for describing predicates.
- cdsl.settings defines classes for describing settings.
- base.settings defines shared settings.
2016-11-08 10:37:17 -08:00
Jakob Stoklund Olesen
ed917c394f Add PEP 484 type annotations to a bunch of Python code.
Along with the mypy tool, this helps find bugs in the Python code
handling the instruction definition data structures.
2016-10-26 15:15:51 -07:00
Jakob Stoklund Olesen
af6355e2ef Move the 'meta' dir to 'lib/cretonne/meta'.
The 'lib/cretonne' directory will be the new root of a stand-alone
cretonne crate containg both Python and Rust sources.

This is in preparation for publishing crates on crates.io.
2016-10-17 14:19:23 -07:00