Commit Graph

18 Commits

Author SHA1 Message Date
Andrew Brown
af1499ce99 Add x86 implementation of shuffle 2019-09-19 10:53:40 -07:00
Andy Wortman
99380fad1a Use 'xor r, r' to set registers to 0 instead of mov (#766) 2019-09-16 16:35:55 +02:00
Andrew Brown
295b2ef614 Avoid extra register movement when lowering an x86 insertlane to a float vector 2019-09-10 10:45:12 -07:00
Ujjwal Sharma
345b2dc0cc [codegen] add new recipe "rout" (#1014)
* [codegen] add new recipe "rout"

Add a new recipe "rout" intended to be used by arithematic operations
that output flags, currently being used for `iadd_cout` and `isub_bout`.

Fixes: https://github.com/CraneStation/cranelift/issues/1009
2019-09-10 12:55:24 +02:00
Benjamin Bouvier
660b8b28b8 [codegen] Add a pinned register that's entirely under the control of the user; 2019-09-06 16:18:27 +02:00
Benjamin Bouvier
d1d2e790b9 [meta] Morph a few pub into pub(crate), and remove dead code; 2019-09-06 15:47:20 +02:00
Benjamin Bouvier
29e3ec51c1 [meta] Introduce the Immediates structure instead of using dynamic lookup; 2019-09-06 15:47:20 +02:00
Ujjwal Sharma
dce8ad8229 [codegen] add encodings for isub borrow variants
Add encodings for isub borrow variants (isub_bout, isub_bin,
isub_borrow) for x86_32, enabling the legalization for isub.i64 to work.

Bug: https://bugzilla.mozilla.org/show_bug.cgi?id=1576675
Bug: https://github.com/CraneStation/cranelift/issues/765
2019-09-05 19:28:33 +02:00
Ujjwal Sharma
ea919489ee [codegen] add encodings for iadd carry variants (#961)
* [codegen] add encodings for iadd carry variants

Add encodings for iadd carry variants (iadd_cout, iadd_cin, iadd_carry)
for x86_32, enabling the legalization for iadd.i64 to work.

* [codegen] remove support for iadd carry variants on riscv

Previously, the carry variants of iadd (iadd_cin, iadd_cout and
iadd_carry) were being legalized for isa/riscv since RISC architectures
lack a flags register.

This forced us to return and accept booleans for these operations, which
proved to be problematic and inconvenient, especially for x86.

This commit removes support for said statements and all dependent
statements for isa/riscv so that we can work on a better legalization
strategy in the future.

* [codegen] change operand type from bool to iflag for iadd carry variants

The type of the carry operands for the carry variants of the iadd
instruction (iadd_cin, iadd_cout, iadd_carry) was bool for compatibility
reasons for isa/riscv. Since support for these instructions on RISC
architectures has been temporarily suspended, we can safely change the
type to iflags.
2019-09-05 15:03:13 +02:00
Andrew Brown
684721ca29 Add x86 recipe for vconst 2019-08-26 16:12:06 -07:00
julian-seward1
b8fb52446c Cranelift: implement redundant fill removal on tree-shaped CFG regions. Mozilla bug 1570584. (#906) 2019-08-25 19:37:34 +02:00
Andrew Brown
6605f308b3 Fix static analysis warnings 2019-08-20 10:21:12 -07:00
Andrew Brown
3fdc78174f Add x86 implementation of extractlane instruction 2019-08-20 10:21:12 -07:00
Carmen Kwan
19257f80c1 Add reference types R32 and R64
-Add resumable_trap, safepoint, isnull, and null instructions
-Add Stackmap struct and StackmapSink trait

Co-authored-by: Mir Ahmed <mirahmed753@gmail.com>
Co-authored-by: Dan Gohman <sunfish@mozilla.com>
2019-08-16 11:35:16 -07:00
Andrew Brown
3b36a1d1d8 Add x86 implementation of insertlane instruction 2019-07-16 17:07:44 -07:00
Andrew Brown
683e7c75a3 Add x86-specific shuffle instructions
This includes both PSHUFD and PSHUFB; these are necessary to legalize future SIMD instructions.
2019-07-16 17:07:44 -07:00
Andrew Brown
61772e9775 Add raw_bitcast instruction
Casts bits as a different type of the same width with no change to the data (unlike bitcast)
2019-07-16 17:07:44 -07:00
Benjamin Bouvier
fd03677292 [meta] Recipes and encodings descriptions for x86; 2019-07-05 11:38:51 +02:00