bjorn3
add6a4f269
Correctly zero extend operand of fcvt_from_uint for 8ints and 16bit ints ( #997 )
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Fixes #996
2019-09-18 10:06:15 +02:00
Andrew Brown
295b2ef614
Avoid extra register movement when lowering an x86 insertlane to a float vector
2019-09-10 10:45:12 -07:00
Andrew Brown
00bedca274
Avoid extra register movement when lowering the x86 extractlane of a float vector
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This commit is based on the assumption that floats are already stored in XMM registers in x86. When extracting a lane, cranelift was moving the float to a regular register and back to an XMM register; this change avoids this by shuffling the float value to the lowest bits of the XMM register. It also assumes that the upper bits can be left as is (instead of zeroing them out).
2019-09-10 10:45:12 -07:00
Nicolas B. Pierron
8edc40cb49
BB-like manual legalization for x86 ISA
2019-07-12 14:20:26 +02:00
Benjamin Bouvier
cd4c28ad97
[meta] Legalization: Unprefix some module paths to make code neater;
2019-07-09 10:56:50 +02:00
Benjamin Bouvier
d7d48d5cc6
Add the dyn keyword before trait objects;
2019-06-24 11:42:26 +02:00
Benjamin Bouvier
18a5386c08
Remove and reorganize IntCC/FloatCC imports to avoid a build warning;
2019-05-02 10:08:53 +02:00
Benjamin Bouvier
95e6fc9efc
Avoid inserting checks during div/rem legalization when the input is a constant immediate;
2019-04-25 16:58:41 +02:00
lazypassion
747ad3c4c5
moved crates in lib/ to src/, renamed crates, modified some files' text ( #660 )
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moved crates in lib/ to src/, renamed crates, modified some files' text (#660 )
2019-01-28 15:56:54 -08:00
