Commit Graph

9 Commits

Author SHA1 Message Date
Andrew Brown
994fe41daf x64: allow vector types in select move
As reported in #3173, the `select` instruction fails an assertion when it is given `v128` types as operands. This change relaxes the assertion to allow the same type of XMM move that occurs for the f32 and f64 types. This fixes #3173 in the old `lower.rs` code temporarily until the relatively complex `select` lowering can be ported to ISLE.
2021-11-19 11:24:30 -08:00
Alex Crichton
88e400b98c Make memory smaller 2021-11-19 08:44:22 -08:00
Alex Crichton
efa3468ff9 x64: Add test for a fixed issue
This commit adds a test from #3337 which is an issue that was fixed
in #3506 due to moving `imul` lowering rules to ISLE which fixed the
underlying issue of accidentally not falling through to the necessary
case for general `i64x2.mul` multiplication.

Closes #3337
2021-11-19 08:16:21 -08:00
Alex Crichton
352ee2b186 Move insertlane to ISLE (#3544)
This also fixes a bug where `movsd` was incorrectly used with a memory
operand for `insertlane`, causing it to actually zero the upper bits
instead of preserving them.

Note that the insertlane logic still exists in `lower.rs` because it's
used as a helper for a few other instruction lowerings which aren't
migrated to ISLE yet. This commit also adds a helper in ISLE itself for
those other lowerings to use when they get implemented.

Closes #3216
2021-11-18 13:48:11 -06:00
Alex Crichton
92394566fc x64: Migrate fabs and bnot vector operations to ISLE
This was my first attempt at transitioning code to ISLE to originally
fix #3327 but that fix has since landed on `main`, so this is instead
now just porting a few operations to ISLE.

Closes #3336
2021-11-16 07:36:49 -08:00
Johnnie Birch
5d5629de60 Fix for issue 3327. Updates Bnot to handle case for NaN float 2021-11-15 18:47:23 -08:00
Johnnie Birch
e3aae9e498 Refactor to avoid too strict assertion. Fix for 3160 and 3161.
Assertion was intended for SIMD lowering of F64x2ConvertLowI32x4U
2021-08-24 19:39:47 -07:00
Alex Crichton
c6b095f9a3 cranelift: Implement nan canonicalization for vectors (#3146)
This fixes some fuzz bugs that came about enabling simd where nan
canonicalization is performed on the fuzzers but cranelift would panic
on these ops for vectors. This adds some custom codegen with `bitselect`
to ensure any nan lanes are canonical-nan lanes in the canonicalized
operations.
2021-08-05 13:44:16 -05:00
Andrew Brown
961c9ea909 test: check unaligned load-coalescing with SIMD operations 2021-07-26 13:39:16 -07:00