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a114423d0a649079586d8081eb854176df9e7fd9
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337 Commits

Author SHA1 Message Date
bjorn3
a114423d0a Remove std feature from cranelift-entity 2019-10-02 11:50:44 -07:00
bjorn3
d25e611946 Remove std feature from cranelift-bforest 2019-10-02 11:50:44 -07:00
Erin Power
dadfbcd32b Re-export ReplaceBuilder 
ReplaceBuilder is available in the public API through
`DataFlowGraph::replace`, however it's documentation is not available
through rustdoc as the type isn't publicly importable.
 2019-10-02 13:56:27 +02:00
Nicolas B. Pierron
e0005f1e6c Insert split-edge of conditional branches before the destination. 2019-10-02 12:03:56 +02:00
bjorn3
093b3b3426 Fix brz.i128 
Fixes #1066
 2019-10-02 11:04:29 +02:00
Benjamin Bouvier
0d50462a93 Fixes #1091: Use match statements instead of HashMaps in x86 encodings; 2019-10-01 09:01:37 -07:00
Andrew Brown
90c49a2f7c Add saturating subtraction with a SIMD encoding 
This includes the new instructions `ssub_sat` and `usub_sat` and only encodes the i8x16 and i16x8 types; these are what is needed for implementing the SIMD spec (see https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#saturating-integer-subtraction).
 2019-09-30 13:54:30 -07:00
Andrew Brown
21144068d4 Add saturating addition with a SIMD encoding 
This includes the new instructions `sadd_sat` and `uadd_sat` and only encodes the i8x16 and i16x8 types; these are what is needed for implementing the SIMD spec (see https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#saturating-integer-addition).
 2019-09-30 13:54:30 -07:00
Andrew Brown
630cb3ee62 Add x86 encoding for SIMD imul 
Only i16x8 and i32x4 are encoded in this commit mainly because i8x16 and i64x2 do not have simple encodings in x86. i64x2 is not required by the SIMD spec and there is discussion (https://github.com/WebAssembly/simd/pull/98#issuecomment-530092217) about removing i8x16.
 2019-09-30 13:54:30 -07:00
Andrew Brown
168ad7fda3 Fix 16-bit x86_pextr encoding 
The x86 ISA has (at least) two encodings for PEXTRW:
 1. in the SSE2 opcode (66 0f c5) the XMM operand uses r/m and the GPR operand uses reg
 2. in the SSE4.1 opcode (66 0f 3a 15) the XMM operand uses reg and the GPR operand uses r/m

This changes the 16-bit x86_pextr encoding from 1 to 2 to match the other PEXTR* implementations (all #2 style).
 2019-09-30 13:54:30 -07:00
Andrew Brown
c932f9b2b5 Add parsing of 16-bit signed integers 2019-09-30 13:54:30 -07:00
Andrew Brown
ba393afd4d Add x86 legalization for SIMD ineg 2019-09-30 13:54:30 -07:00
Andrew Brown
ca1df499a0 Add x86 encoding for isub 2019-09-30 13:54:30 -07:00
Benjamin Bouvier
4e3cb25983 Use a sorted array for (Ebb, Inst) interval again (fixes #1084); 2019-09-30 16:25:41 +02:00
John Gallagher
79784dfaf6 Change signature of all() function 2019-09-30 16:09:40 +02:00
Benjamin Bouvier
c3d01756a3 Baldrdash: uses ECX for the WasmTableCallSigReg on x86 32-bits; 2019-09-30 15:11:06 +02:00
Ujjwal Sharma
9f3c5b967e [codegen] add documentation for overflow 
Add documentation to the icmp instruction text for both signed and
unsigned overflow, making it very clear why unsigned overflow is
complicated and where to find it.
 2019-09-27 16:29:16 -07:00
Joshua Nelson
a1f6457e8a Allow building without std (#1069) 
Closes https://github.com/CraneStation/cranelift/issues/1067
 2019-09-26 18:00:03 +02:00
Sean Stangl
3d5346a90b Name opcodes statically in isa/x86. Closes #1051 (#1079) 2019-09-25 19:59:49 -06:00
Benjamin Bouvier
46ab1b4103 Liverange: use a macro to make Order comparisons simpler to read; 2019-09-25 11:43:29 +02:00
Benjamin Bouvier
5beb10e77a Regalloc: remove the transient LiveRangeContext data structure; 2019-09-25 11:43:29 +02:00
Benjamin Bouvier
b9b1c842e9 Use LiveRange::reaches_use instead of reimplementing it in liveness checks; 2019-09-25 11:43:29 +02:00
Benjamin Bouvier
59f5f12c60 [codegen] Rename GenLiveRange to GenericLiveRange; 
(to avoid confuson with Gen interpreted as Generator)
 2019-09-25 11:43:29 +02:00
Benjamin Bouvier
b036ab77dc Update comment about the live range implementation details; 2019-09-25 11:43:29 +02:00
Ujjwal Sharma
43a891dfa2 [codegen] add intcc conditions for reading overflow flag 
Add conditions to IntCC for checking the overflow flag (Overflow,
NotOverflow).
 2019-09-25 11:42:58 +02:00
Dan Gohman
dfdd504edc Bump version to 0.44.0 2019-09-24 16:28:17 -07:00
Ujjwal Sharma
6e131e5347 [codegen] add intcc conditions for reading carry flag 
Add conditions to IntCC for checking the carry flag (Carry, NotCarry).

Fixes: https://github.com/CraneStation/cranelift/issues/980
 2019-09-24 15:12:09 -07:00
Artur Jamro
1431ab5201 Derive serde traits for TrapCode 2019-09-24 10:50:52 -07:00
Andrew Brown
636ef98024 Use existing is_equal predicate with the newly-shared condition codes 
This removes the `HasConditionCode(&'static str)` predicate and the associated issues with that.
 2019-09-24 09:33:07 -07:00
Andrew Brown
c648fa3d06 Move condcodes.rs to a new crate, cranelift-codegen-shared 
This move allows the `IntCC`/`FloatCC` enums to be used in both meta (for predicate matching) and in codegen. To avoid breaking any code dependent on the previous location of condcodes.rs (`cranelift-codegen/src/condcodes.rs`), the module is re-exported under `cranelift_codegen::ir`.
 2019-09-24 09:33:07 -07:00
Andrew Brown
a3db30d97e Add x86 encoding for SIMD icmp eq 
Also adds a predicate for matching the `eq` IntCC code (TODO this should be replaced by something more general)
 2019-09-24 09:33:07 -07:00
Andrew Brown
702155b19b Optimize vconst for x86 when immediate contains all zeroes or ones 
Instead of using MOVUPS to expensively load bits from memory, this change uses a predicate to optimize vconst without a memory access:
 - when the 128-bit immediate is all zeroes in all bits, use PXOR to zero out an XMM register
 - when the 128-bit immediate is all ones in all bits, use PCMPEQB to set an XMM register to all ones

This leaves the constant data in the constant pool, which may increase code size (TODO)
 2019-09-24 09:33:07 -07:00
Nicolas B. Pierron
694de912a5 Update brnz.i128 legalization to use non-extended basic blocks. 2019-09-24 15:55:58 +02:00
Nicolas B. Pierron
26cfbafb32 Add ebb macro to insert a new blocks in legalization output. 2019-09-24 15:55:58 +02:00
Nicolas B. Pierron
0c1f17d6dd Add empty_vararg literal to generate jump instruction. 2019-09-24 15:55:58 +02:00
Nicolas B. Pierron
614fb7b526 Factor out the var_index function. 2019-09-24 15:55:58 +02:00
Erin Power
947fce194e Replaced instances of SparseSet with EntitySet 2019-09-23 17:20:25 +02:00
Benjamin Bouvier
f0244516c5 [meta] Make more things pub(crate) instead of pub; 
This could help the compiler find unused fields/methods. It didn't find any
during this migration.
 2019-09-23 14:42:20 +02:00
Benjamin Bouvier
c2587c9d61 [meta] Remove Literal's kind field; 2019-09-23 14:42:20 +02:00
Benjamin Bouvier
3ab8eed7d3 Remove unused core::mem import; 2019-09-23 14:41:07 +02:00
Anthony Ramine
26accbadf8 Use f32::to_bits and f64::to_bits 2019-09-23 10:36:03 +02:00
Anthony Ramine
178241625c Use slice::from_ref and slice::from_mut 2019-09-23 10:36:03 +02:00
Dan Gohman
411545ed9a Bump version to 0.43.1 2019-09-20 14:11:15 -07:00
Andrew Brown
2330ca7e2c Fix incorrect regmove and fill encodings for SIMD types 
- `fill` attempted to use a GPR recipe, `fillSib32`, instead of its FPR equivalent, `ffillSib32` (code compiled without error but incorrect instructions were allowed, e.g. `v1 = regmove v0, %rdi -> %xmm0`
- `regmove` could be encoded with a GPR recipe, `rmov`, which hid the above incorrectness; now only FPR-to-FPR regmoves are allowed using the `frmov` recipe
 2019-09-20 14:02:03 -07:00
Nick Fitzgerald
9b8e7b511e tidy: Remove extra semicolons 
These were causing compilation warnings.
 2019-09-19 16:25:49 -07:00
Dan Gohman
5c5eabb8d0 Bump version to 0.43.0 2019-09-19 12:23:51 -07:00
Andrew Brown
fe25abeb0d Add x86 encodings for vector copy, copy_nop, fill_nop 2019-09-19 12:04:14 -07:00
Andrew Brown
766cf8ddfd Add x86 implemention for SIMD iadd 2019-09-19 12:04:14 -07:00
Andrew Brown
cd426cb7bc Rename Uimm128 to V128Imm 2019-09-19 12:04:14 -07:00
Andrew Brown
7e6913e362 Add x86 encodings for vector store, load, fill, spill, and regmove 2019-09-19 12:04:14 -07:00