Commit Graph

8 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
9fbfd0d2a6 Remove the vconst instruction and the UnaryImmVector format.
No instruction sets actually have single instructions for materializing
vector constants. You always need to use a constant pool.

Cretonne doesn't have constant pools yet, but it will in the future, and
that is how vector constants should be represented.
2017-03-10 11:57:49 -08:00
Jakob Stoklund Olesen
c50e5f3f66 Separate immediate and value operands in the instruction format.
Instruction formats are now identified by a signature that doesn't
include the ordering of value operands relative to immediate operands.

This means that the BinaryRev instruction format becomes redundant, so
delete it. The isub_imm instruction was the only one using that format.
Rename it to irsub_imm to make it clear what it does now that it is
printed as 'irsub_imm v2, 45'.
2017-03-10 11:20:39 -08:00
Jakob Stoklund Olesen
ecc46e56e1 Add is_call and is_return instruction attributes. 2017-03-08 14:48:50 -08:00
Jakob Stoklund Olesen
fd58b7cc29 Add vsplit and vconcat instructions.
Add support for two new type variable functions: half_vector() and
double_vector().

Use these two instructions to break down unsupported SIMD types and
build them up again.
2017-03-07 14:31:57 -08:00
Angus Holder
855c429d31 Documentation fix for what appears to be a minor copy-paste mistake. 2017-02-22 09:33:17 -08:00
Jakob Stoklund Olesen
b6fa40d6a3 Add a return_reg instruction to the base instruction set.
Register-style return is used by all RISC architectures, so it is
natural to have a shared instruction representation.
2017-02-21 13:05:17 -08:00
Dominik Inführ
8285f2a672 added Opcode flags methods
generate `is_branch`, `is_terminator`, `can_trap` methods for `enum
Opcode`.
2016-12-02 15:50:28 -08:00
Jakob Stoklund Olesen
0b9b956695 Split out instruction definitions.
- cdsl.instructions defines the Instruction class.
- base.instructions defines the base instruction set.
2016-11-08 12:33:50 -08:00