Jakob Stoklund Olesen
9c23196049
Implement binary emission of RISC-V return instructions.
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The return address is now always supplied in %x1, so the return address
predictor will recognize the jalr as a return and not some indirect
branch.
2017-04-19 16:26:04 -07:00
Jakob Stoklund Olesen
1c890f317d
Add RISC-V call instruction encodings.
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Calls are jal with a fixed %x1 link register.
2017-04-11 10:40:38 -07:00
Jakob Stoklund Olesen
d2f575b54a
Add jump encodings to RISC-V.
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Fix a bug in gen_encoding.py when dealing with non-polymorphic
instructions where the type variable is None in Python, VOID in Rust.
2017-04-06 15:17:57 -07:00
Jakob Stoklund Olesen
1440b673fc
Use EBB offsets for encoding RISC-V branches.
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Stop emitting EBB relocations. Use the offsets computed by
relax_branches() to encode the correct displacements immediately.
2017-04-06 12:55:57 -07:00
Jakob Stoklund Olesen
8353651559
rustfmt 0.8.1
2017-04-05 09:00:11 -07:00
Jakob Stoklund Olesen
3a47b40ff8
Add RISC-V encodings for brz and brnz.
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These branches compare a register to zero. RISC-V implements this with
the %x0 hard-coded zero register.
2017-04-03 15:20:57 -07:00
Jakob Stoklund Olesen
39e102b155
Add conditional branch encodings for RISC-V.
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Not all br_icmp opcodes are present in the ISA. The missing ones can be
reached by commuting operands.
Don't attempt to encode EBB offsets yet. For now just emit an EBB
relocation for the branch instruction.
2017-04-03 15:16:25 -07:00
Jakob Stoklund Olesen
175b269760
Add RISC-V encodings for lui.
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This instruction can materialize constants with the low 12 bits clear.
2017-04-03 12:27:22 -07:00
Jakob Stoklund Olesen
c13c318ec4
Add icmp_imm encodings for RISC-V.
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The ISA has icmp_imm slt/ult with 12-bit signed immediate operands.
2017-04-03 10:59:28 -07:00
Jakob Stoklund Olesen
8187fd7371
Emit Rshamt-type instructions for RISC-V.
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These are the shift-by-immediate instructions.
2017-03-31 15:33:21 -07:00
Jakob Stoklund Olesen
7c9d187b6d
Emit I-type instructions for RISC-V.
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These are the BinaryImm formats.
2017-03-31 15:15:20 -07:00
Jakob Stoklund Olesen
39fc0eb3cf
Add RISC-V encodings for supported icmp variants.
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Only slt and ult variants are in the instruction set. Other condition
codes must be synthesized.
2017-03-31 13:47:07 -07:00
Jakob Stoklund Olesen
ca2b1c79d7
Generate binemit::emit_inst() functions.
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Use the meta language encoding recipes to generate an emit_inst()
function for each ISA. The generated calls into recipe_*() functions
that must be implemented by hand.
Implement recipe_*() functions for the RISC-V recipes.
Add the TargetIsa::emit_inst() entry point which emits an instruction to
a CodeSink trait object.
2017-03-28 14:44:36 -07:00
