Commit Graph

6 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
608d452f0c Compute the controlling type variable accurately.
Some polymorphic instructions don't return the controlling type
variable, so it has to be computed from the designated operand instead.

- Add a requires_typevar_operand() method to the operand constraints
  which indicates that.
- Add a ctrl_typevar(dfg) method to InstructionData which computes the
  controlling type variable correctly, and returns VOID for monomorphic
  instructions.
- Use ctrl_typevar(dfg) to drive the level-1 encoding table lookups.
2017-02-21 16:26:19 -08:00
Jakob Stoklund Olesen
1fa3ddf018 Return RegInfo by value from TargetIsa::register_info().
The struct is just a pair of static references, and we don't need the
double indirection.
2017-02-14 16:05:54 -08:00
Jakob Stoklund Olesen
933dfc70c1 Fix a dead code warning from the new Rust compiler.
On ISAs with no instruction predicates, just emit an unimplemented!()
stub for the check_instp() function. It is unlikely that a finished ISA
will not have any instruction predicates.
2017-02-03 11:28:59 -08:00
Jakob Stoklund Olesen
2390e3e3f0 Add operand register constraints.
Every encoding recipe must specify register constraints on input and
output values.

Generate recipe constraint tables along with the other encoding tables.
2017-01-25 13:35:18 -08:00
Jakob Stoklund Olesen
1d21422032 Generate register class descriptors.
Add a mechanism for defining sub-classes of register classes.
2017-01-20 14:23:06 -08:00
Jakob Stoklund Olesen
fb4db38dd6 Fill in boilerplate for Intel and ARM targets.
The intel, arm32, and arm32 targets were only defined in the meta
language previously. Add Rust implementations too.

This is mostly boilerplate, except for the unit tests in the
registers.rs files.
2016-11-23 10:42:07 -08:00