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16 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
4ee519e620 Add RISC-V call instruction encodings. 
Calls are jal with a fixed %x1 link register.
 2017-04-11 10:40:38 -07:00
Jakob Stoklund Olesen
51dea9f784 Syntax tweak: Omit comma after an initial enum immediate. 
This affects the comparison instructions which now read "icmp ult a, b".
This mimics LLVM's style and makes it simpler to add instruction flags
in the future, such as "load v1" -> "load aligned v1".

These enumerated operands and flags feel like opcode modifiers rather
than value operands, so displaying them differently makes sense.

Value and numeric operands are still comma separated.
 2017-04-10 10:28:37 -07:00
Jakob Stoklund Olesen
896ac935b9 Add jump encodings to RISC-V. 
Fix a bug in gen_encoding.py when dealing with non-polymorphic
instructions where the type variable is None in Python, VOID in Rust.
 2017-04-06 15:17:57 -07:00
Jakob Stoklund Olesen
fa4f151b9b Add a fallthrough instruction. 
Change jumps to fallthroughs in the branch relaxation pass before
computing the EBB offsets.
 2017-04-06 14:22:32 -07:00
Jakob Stoklund Olesen
856a67ca3a Use EBB offsets for encoding RISC-V branches. 
Stop emitting EBB relocations. Use the offsets computed by
relax_branches() to encode the correct displacements immediately.
 2017-04-06 12:55:57 -07:00
Jakob Stoklund Olesen
8a3f538441 Fix a bug in the binemit file test. 
Only emit each instruction once, or the offset computations go all
wrong.
 2017-04-06 11:17:46 -07:00
Jakob Stoklund Olesen
e641c97670 Add RISC-V encodings for brz and brnz. 
These branches compare a register to zero. RISC-V implements this with
the %x0 hard-coded zero register.
 2017-04-03 15:20:57 -07:00
Jakob Stoklund Olesen
479ff156c1 Add conditional branch encodings for RISC-V. 
Not all br_icmp opcodes are present in the ISA. The missing ones can be
reached by commuting operands.

Don't attempt to encode EBB offsets yet. For now just emit an EBB
relocation for the branch instruction.
 2017-04-03 15:16:25 -07:00
Jakob Stoklund Olesen
0530e822d4 Add RISC-V encodings for lui. 
This instruction can materialize constants with the low 12 bits clear.
 2017-04-03 12:27:22 -07:00
Jakob Stoklund Olesen
4e398164d2 Add icmp_imm encodings for RISC-V. 
The ISA has icmp_imm slt/ult with 12-bit signed immediate operands.
 2017-04-03 10:59:28 -07:00
Jakob Stoklund Olesen
9ddbc5d861 Emit Rshamt-type instructions for RISC-V. 
These are the shift-by-immediate instructions.
 2017-03-31 15:33:21 -07:00
Jakob Stoklund Olesen
c9a14448b8 Emit I-type instructions for RISC-V. 
These are the BinaryImm formats.
 2017-03-31 15:15:20 -07:00
Jakob Stoklund Olesen
e9907fbdd6 Add RISC-V encodings for supported icmp variants. 
Only slt and ult variants are in the instruction set. Other condition
codes must be synthesized.
 2017-03-31 13:47:07 -07:00
Jakob Stoklund Olesen
4613cbcf18 Test binary encodings of some RV32I instructions. 
These are the R-format instructions in RV32I.
 2017-03-29 13:16:12 -07:00
Jakob Stoklund Olesen
6ad34f90aa Allow for unencoded instructions in the binemit tests. 
If an instruction doesn't have an associated encoding, use the standard
TargetIsa hook to encode it.

The test still fails if an instruction can't be encoded. There is no
legalization step.
 2017-03-29 09:55:49 -07:00
Jakob Stoklund Olesen
f540cb0664 Add a binemit test command. 
This makes it possible to write file tests that verify the binary
encoding of machine code.
 2017-03-28 15:56:30 -07:00