It appears that having the meta directory crate be inside the codegen
directory is not enough to allow codegen to depend on it without it
being published. So, let's just publish it.
- don't generate "&& true" when generating instruction eq() fn;
- use more Self;
- use subsec_millis instead of subsec_nanos and divide;
- coalesce two ifs;
* Don't implement Eq and Hash for EntityList
* Generate eq and hash methods for InstructionData
* Use the eq() and hash() methods of InstructionData in simple_gvn
The documentation for these instructions suggests that immediate values
which could lead to trapping should be invalid.
While it seems nice to have these instructions be always non-trapping,
it's also nice to say that the `_imm` forms of instructions are
interchangeable with the corresponding non-`_imm` forms accompanied
by `iconst` instructions.
This requires splitting X86PCRel4 into two separate relocations, to
distinguish the case where the instruction is a call, as Mach-O uses a
different relocation in that case.
This also makes it explicit that only x86-64 relocations are supported
currently.
`urm_noflags` is a variant of `urm` which doesn't clobber the flags, and
`urm_noflags_abcd` is a further variant for ABCD registers, so it also
doesn't clobber the flags.
This switches from a custom list of architectures to use the
target-lexicon crate.
- "set is_64bit=1; isa x86" is replaced with "target x86_64", and
similar for other architectures, and the `is_64bit` flag is removed
entirely.
- The `is_compressed` flag is removed too; it's no longer being used to
control REX prefixes on x86-64, ARM and Thumb are separate
architectures in target-lexicon, and we can figure out how to
select RISC-V compressed encodings when we're ready.
* Optimize 0.0 floating point constants. Rather than using the existing
process of emitting bit patterns and moving them into floating point
registers, use the `xorps` instruction to zero out the register.
* is_zero predicate function will not accept negative zero. Fixed formatting for encoding recipe and filetests.
* Start adding the load_complex and store_complex instructions.
N.b.:
The text format is not correct yet. Requires changes to the lexer and parser.
I'm not sure why I needed to change the RuntimeError to Exception yet. Will fix.
* Get first few encodings of load_complex working. Still needs var args type checking.
* Clean up ModRM helper functions in binemit.
* Implement 32-bit displace for load_complex
* Use encoding helpers instead of doing them all by hand
* Initial implementation of store_complex
* Parse value list for load/store_complex with + as delimiter. Looks nice.
* Add sign/zero-extension and size variants for load_complex.
* Add size variants of store_complex.
* Add asm helper lines to load/store complex bin tests.
* Example of length-checking the instruction ValueList for an encoding. Extremely questionable implementation.
* Fix Python linting issues
* First draft of postopt pass to fold adds and loads into load_complex. Just simple loads for now.
* Optimization pass now works with all types of loads.
* Add store+add -> store_complex to postopt pass
* Put complex address optimization behind ISA flag.
* Add load/store complex for f32 and f64
* Fixes changes to lexer that broke NaN parsing.
Abstracts away the repeated checks for whether or not the characters
following a + or - are going to be parsed as a number or not.
* Fix formatting issues
* Fix register restrictions for complex addresses.
* Encoding tests for x86-32.
* Add documentation for newly added instructions, recipes, and cdsl changes.
* Fix python formatting again
* Apply value-list length predicates to all LoadComplex and StoreComplex instructions.
* Add predicate types to new encoding helpers for mypy.
* Import FieldPredicate to satisfy mypy.
* Add and fix some "asm" strings in the encoding tests.
* Line-up 'bin' comments in x86/binary64 test
* Test parsing of offset-less store_complex instruction.
* 'sNaN' not 'sNan'
* Bounds check the lookup for polymorphic typevar operand.
* Fix encodings for istore16_complex.
* initial set of work for windows fastcall (x64) call convention
- call conventions: rename `fastcall` to `windows_fastcall`
- add initial set of filetests
- ensure arguments are written after the shadow space/store (offset-wise)
The shadow space available before the arguments (range 0..32)
is not used as spill space yet.
* address review feedback
* x86 recipes: emit StackOverflow trap for all sp-relative loads and stores
* x86 recipes: emit StackOverflow trap for push and pop
* x86 binary filetests: add stk_ovf trap annotations
* Remove the mypy version constraint and set strict_optional to False.
* Add type annotations for `ISA` variables.
mypy 0.600 seems to require explicit annotations here.
* Annotate the ISA variables in the defs.py files too.
regmove, regfill, and regspill have immediates which aren't value
operands, so they aren't in the set of things that can be described by
the existing constraint system. Consequently, constraints saying that
the non-REX encodings only support registers that don't need REX
prefixes don't work. Fow now, just remove the non-REX encodings, so
that they don't get selected when they aren't valid.
This fixes the last known issue with instruction shrinking, so it can
be re-enabled.
Add a calling-convention setting to the `Flags` used as part of the
`TargetIsa`. This allows Cretonne code that generates calls to use the
correct convention, such as when emitting libcalls during legalization
or when the wasm frontend is decoding functions. This setting can be
overridden per-function.
This also adds "fast", "cold", and "fastcall" conventions, with "fast"
as the new default. Note that "fast" and "cold" are not intended to be
ABI-compatible across Cretonne versions.
This will also ensure Windows users will get an `unimplemented!` rather
than silent calling-convention mismatches, which reflects the fact that
Windows calling conventions are not yet implemented.
This also renames SpiderWASM, which isn't camel-case, to Baldrdash,
which is, and which is also a more relevant name.
