Commit Graph

60 Commits

Author SHA1 Message Date
Nick Fitzgerald
8c5f59c0cf wasmtime: Implement table.get and table.set
These instructions have fast, inline JIT paths for the common cases, and only
call out to host VM functions for the slow paths. This required some changes to
`cranelift-wasm`'s `FuncEnvironment`: instead of taking a `FuncCursor` to insert
an instruction sequence within the current basic block,
`FuncEnvironment::translate_table_{get,set}` now take a `&mut FunctionBuilder`
so that they can create whole new basic blocks. This is necessary for
implementing GC read/write barriers that involve branching (e.g. checking for
null, or whether a store buffer is at capacity).

Furthermore, it required that the `load`, `load_complex`, and `store`
instructions handle loading and storing through an `r{32,64}` rather than just
`i{32,64}` addresses. This involved making `r{32,64}` types acceptable
instantiations of the `iAddr` type variable, plus a few new instruction
encodings.

Part of #929
2020-06-30 12:00:57 -07:00
Benjamin Bouvier
c9a3f05afd machinst x64: implement calls and int cmp/store/loads;
This makes it possible to run a simple recursive fibonacci function in
wasmtime.
2020-06-25 16:20:33 +02:00
Benjamin Bouvier
dad56a2488 cranelift: add a new resumable_trapnz instruction;
This is useful to have to allow resumable_trap to happen in loop
headers, for instance. This is the correct way to implement interrupt
checks in Spidermonkey, which are effectively resumable traps. Previous
implementation was using traps, which is wrong, since traps semantically
can't be resumed after.
2020-06-15 12:04:28 +02:00
Andrew Brown
0dd77d36f8 Rename BinaryImm format to BinaryImm64 2020-05-29 19:56:27 -07:00
Andrew Brown
a27a079d65 Replace ExtractLane format with BinaryImm8
Like https://github.com/bytecodealliance/wasmtime/pull/1762, this change the name of the `ExtractLane` format to the more-general `BinaryImm8` and renames its immediate argument from `lane` to `imm`.
2020-05-29 19:56:27 -07:00
Andrew Brown
7d6e94b952 Replace InsertLane format with TernaryImm8
The InsertLane format has an ordering (`value().imm().value()`) and immediate name (`"lane"`) that make it awkward to use for other instructions. This changes the ordering (`value().value().imm()`) and uses the default name (`"imm"`) throughout the codebase.
2020-05-29 19:56:27 -07:00
Andrew Brown
c92917de15 Fix typo in sadd_sat instruction definition 2020-05-26 09:55:26 +02:00
Andrew Brown
a312506262 Add x86 complex encodings for SIMD load-extend instructions 2020-04-30 11:38:01 -07:00
Andrew Brown
65856987cd Add const_addr instruction
This new instruction calculates the effective address of a constant in the constant pool using LEA (x86).
2020-04-17 11:59:47 -07:00
Andrew Brown
cf1cfdcace Add new instructions to support SIMD load_extend 2020-03-31 11:35:26 -07:00
Andrew Brown
fa7481a681 Add x86 implementation of SIMD swizzle instruction 2020-03-06 15:49:53 -08:00
Andrew Brown
6e0401b83a Refactor SIMD lane instructions to separate define* function 2020-03-06 14:57:11 -08:00
bjorn3
0a1bb3ba6c Add TLS support for ELF and MachO (#1174)
* Add TLS support
* Add binemit and legalize tests
* Spill all caller-saved registers when necessary
2020-02-25 17:50:04 -08:00
Andrew Brown
032e81fd6f Add x86 SIMD average rounding 2020-02-24 09:48:38 -08:00
Andrew Brown
3ae1af1ad2 Add new Cranelift instructions for integer min/max
This includes legalizations to the previously-existing x86 SIMD integer min/max.
2020-02-21 09:33:43 -08:00
Ryan Hunt
832666c45e Mass rename Ebb and relatives to Block (#1365)
* Manually rename BasicBlock to BlockPredecessor

BasicBlock is a pair of (Ebb, Inst) that is used to represent the
basic block subcomponent of an Ebb that is a predecessor to an Ebb.

Eventually we will be able to remove this struct, but for now it
makes sense to give it a non-conflicting name so that we can start
to transition Ebb to represent a basic block.

I have not updated any comments that refer to BasicBlock, as
eventually we will remove BlockPredecessor and replace with Block,
which is a basic block, so the comments will become correct.

* Manually rename SSABuilder block types to avoid conflict

SSABuilder has its own Block and BlockData types. These along with
associated identifier will cause conflicts in a later commit, so
they are renamed to be more verbose here.

* Automatically rename 'Ebb' to 'Block' in *.rs

* Automatically rename 'EBB' to 'block' in *.rs

* Automatically rename 'ebb' to 'block' in *.rs

* Automatically rename 'extended basic block' to 'basic block' in *.rs

* Automatically rename 'an basic block' to 'a basic block' in *.rs

* Manually update comment for `Block`

`Block`'s wikipedia article required an update.

* Automatically rename 'an `Block`' to 'a `Block`' in *.rs

* Automatically rename 'extended_basic_block' to 'basic_block' in *.rs

* Automatically rename 'ebb' to 'block' in *.clif

* Manually rename clif constant that contains 'ebb' as substring to avoid conflict

* Automatically rename filecheck uses of 'EBB' to 'BB'

'regex: EBB' -> 'regex: BB'
'$EBB' -> '$BB'

* Automatically rename 'EBB' 'Ebb' to 'block' in *.clif

* Automatically rename 'an block' to 'a block' in *.clif

* Fix broken testcase when function name length increases

Test function names are limited to 16 characters. This causes
the new longer name to be truncated and fail a filecheck test. An
outdated comment was also fixed.
2020-02-07 10:46:47 -06:00
Ryan Hunt
bbc0a328c7 Codegen: Allow encoding of (r32|r64).(load|store)
Accessing Wasm reference globals that are reference types will
want to use the plain load/store instructions. This commit adds
encodings for these instructions to match loading a i32/i64.
Producers of IR are required to insert the appropriate barriers
around the loads/stores.
2020-01-23 13:37:11 -06:00
Ryan Hunt
848baa0aa7 Codegen: Add ref.is_invalid instruction
Spidermonkey returns a sentinel ref value of '-1' from some VM functions
to indicate failure. This commit adds an instruction analagous to ref.is_null
that checks for this value.
2020-01-23 13:37:11 -06:00
Benjamin Bouvier
3a4b1cc989 Split define encodings + start splitting instruction definitions (#1322)
* [meta] Split the x86 encodings define function into smaller ones;
* [meta] Start splitting instruction definitions into smaller functions;
2020-01-08 09:38:40 -08:00
Benjamin Bouvier
4632d35196 [meta] Remove the OperandBuilder, replace it with Operand ctors; 2019-10-30 18:39:20 +01:00
Peter Huene
9f506692c2 Fix clippy warnings.
This commit fixes the current set of (stable) clippy warnings in the repo.
2019-10-24 17:20:12 -07:00
Andrew Brown
879ccf871a Add x86 SIMD vall_true
In order to implement SIMD's all_true (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#all-lanes-true), we must legalize some instruction (I chose `vall_true`) to a comparison against 0 and a similar reduction as vany_true using `PTEST` and `SETNZ`. Since `icmp` only allows integers but `vall_true` could allow more vector types, `raw_bitcast` is used to convert the lane types into integers, e.g. b32x4 to i32x4. To do so without runtime type-checking, the `raw_bitcast` instruction (which emits no instruction) can now bitcast from any vector type to the same type, e.g. i32x4 to i32x4.
2019-10-22 11:01:05 -07:00
Andrew Brown
186effc420 Add x86 SIMD vany_true and x86_ptest
In order to implement SIMD's any_true (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#any-lane-true), we must legalize some instruction (I chose `vany_true`) to a sequence of `PTEST` and `SETNZ`. To emit `PTEST` I added the new CLIF instruction `x86_ptest` and used CLIF's `trueif ne` for `SETNZ`.
2019-10-22 11:01:05 -07:00
Benjamin Bouvier
0243b642e3 [meta] Remove name lookups in formats;
This does a lot at once, since there was no clear way to split the three
commits:

- Instruction need to be passed an explicit InstructionFormat,
- InstructionFormat deduplication is checked once all entities have been
defined;
2019-10-22 14:05:12 +02:00
Benjamin Bouvier
d3e694fbe7 [meta] Remove unused InstructionGroup::{name, doc}; 2019-10-22 14:05:12 +02:00
Andrew Brown
b927c55511 Add SIMD bitselect instruction and x86 legalization
This new instructions matches the `bitselect` behavior described in the WASM SIMD spec (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#bitwise-select)
2019-10-17 15:49:29 -07:00
Andrew Brown
90c49a2f7c Add saturating subtraction with a SIMD encoding
This includes the new instructions `ssub_sat` and `usub_sat` and only encodes the i8x16 and i16x8 types; these are what is needed for implementing the SIMD spec (see https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#saturating-integer-subtraction).
2019-09-30 13:54:30 -07:00
Andrew Brown
21144068d4 Add saturating addition with a SIMD encoding
This includes the new instructions `sadd_sat` and `uadd_sat` and only encodes the i8x16 and i16x8 types; these are what is needed for implementing the SIMD spec (see https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#saturating-integer-addition).
2019-09-30 13:54:30 -07:00
Andrew Brown
630cb3ee62 Add x86 encoding for SIMD imul
Only i16x8 and i32x4 are encoded in this commit mainly because i8x16 and i64x2 do not have simple encodings in x86. i64x2 is not required by the SIMD spec and there is discussion (https://github.com/WebAssembly/simd/pull/98#issuecomment-530092217) about removing i8x16.
2019-09-30 13:54:30 -07:00
Andrew Brown
ba393afd4d Add x86 legalization for SIMD ineg 2019-09-30 13:54:30 -07:00
Ujjwal Sharma
9f3c5b967e [codegen] add documentation for overflow
Add documentation to the icmp instruction text for both signed and
unsigned overflow, making it very clear why unsigned overflow is
complicated and where to find it.
2019-09-27 16:29:16 -07:00
Ujjwal Sharma
43a891dfa2 [codegen] add intcc conditions for reading overflow flag
Add conditions to IntCC for checking the overflow flag (Overflow,
NotOverflow).
2019-09-25 11:42:58 +02:00
Ujjwal Sharma
6e131e5347 [codegen] add intcc conditions for reading carry flag
Add conditions to IntCC for checking the carry flag (Carry, NotCarry).

Fixes: https://github.com/CraneStation/cranelift/issues/980
2019-09-24 15:12:09 -07:00
Andrew Brown
af1499ce99 Add x86 implementation of shuffle 2019-09-19 10:53:40 -07:00
Ujjwal Sharma
3418fb6e18 [codegen] reintroduce support for carry and borrow instructions in RI… (#1005)
Reintroduce support for iadd carry variants and isub borrow variants for
RISC ISAs which had been removed in
https://github.com/CraneStation/cranelift/pull/961 and
https://github.com/CraneStation/cranelift/pull/962 because of the lack
of a proper flags register in RISC architectures.
2019-09-13 17:27:49 +02:00
Andrew Brown
6f1ed94e82 Fix documentation 2019-09-10 10:45:12 -07:00
bjorn3
c9a25abbc4 Basic i128 support 2019-09-07 09:55:09 -07:00
Benjamin Bouvier
660b8b28b8 [codegen] Add a pinned register that's entirely under the control of the user; 2019-09-06 16:18:27 +02:00
Benjamin Bouvier
d1d2e790b9 [meta] Morph a few pub into pub(crate), and remove dead code; 2019-09-06 15:47:20 +02:00
Benjamin Bouvier
8fba449b7b [meta] Introduce the EntityRefs structure instead of using dynamic lookup; 2019-09-06 15:47:20 +02:00
Benjamin Bouvier
29e3ec51c1 [meta] Introduce the Immediates structure instead of using dynamic lookup; 2019-09-06 15:47:20 +02:00
Ujjwal Sharma
1a099f2e8c [codegen] change operand type from bool to iflag for isub borrow variants
The type of the borrow operands for the borrow variants of the isub
instruction (isub_bin, isub_bout, isub_borrow) was bool for compatibility
reasons for isa/riscv. Since support for these instructions on RISC
architectures has been temporarily suspended, we can safely change the
type to iflags.
2019-09-05 19:28:33 +02:00
Ujjwal Sharma
ea919489ee [codegen] add encodings for iadd carry variants (#961)
* [codegen] add encodings for iadd carry variants

Add encodings for iadd carry variants (iadd_cout, iadd_cin, iadd_carry)
for x86_32, enabling the legalization for iadd.i64 to work.

* [codegen] remove support for iadd carry variants on riscv

Previously, the carry variants of iadd (iadd_cin, iadd_cout and
iadd_carry) were being legalized for isa/riscv since RISC architectures
lack a flags register.

This forced us to return and accept booleans for these operations, which
proved to be problematic and inconvenient, especially for x86.

This commit removes support for said statements and all dependent
statements for isa/riscv so that we can work on a better legalization
strategy in the future.

* [codegen] change operand type from bool to iflag for iadd carry variants

The type of the carry operands for the carry variants of the iadd
instruction (iadd_cin, iadd_cout, iadd_carry) was bool for compatibility
reasons for isa/riscv. Since support for these instructions on RISC
architectures has been temporarily suspended, we can safely change the
type to iflags.
2019-09-05 15:03:13 +02:00
Benjamin Bouvier
49a37e48fb [codegen] Make scalar_to_vector's output type a lane of its input type; 2019-09-04 19:09:54 +02:00
Andrew Brown
407d24c013 Add operand kind and format for unsigned 128-bit immediates 2019-08-26 16:12:06 -07:00
julian-seward1
b8fb52446c Cranelift: implement redundant fill removal on tree-shaped CFG regions. Mozilla bug 1570584. (#906) 2019-08-25 19:37:34 +02:00
Carmen Kwan
19257f80c1 Add reference types R32 and R64
-Add resumable_trap, safepoint, isnull, and null instructions
-Add Stackmap struct and StackmapSink trait

Co-authored-by: Mir Ahmed <mirahmed753@gmail.com>
Co-authored-by: Dan Gohman <sunfish@mozilla.com>
2019-08-16 11:35:16 -07:00
Benjamin Bouvier
627ba24b59 Simplify jump table instructions and add missing conversion;
This makes non-legalized jump table instructions operate on operands with
pointer-sized types. This means we need to extend smaller types into the
pointer-sized operand, when the two don't match.
2019-08-02 18:39:39 +02:00
Andrew Brown
61772e9775 Add raw_bitcast instruction
Casts bits as a different type of the same width with no change to the data (unlike bitcast)
2019-07-16 17:07:44 -07:00
Andrew Brown
5f0e5567c1 Add scalar_to_vector instruction
Moves scalar values in a GPR register to an FPR register
2019-07-16 17:07:44 -07:00