Jakob Stoklund Olesen
896ac935b9
Add jump encodings to RISC-V.
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Fix a bug in gen_encoding.py when dealing with non-polymorphic
instructions where the type variable is None in Python, VOID in Rust.
2017-04-06 15:17:57 -07:00
Jakob Stoklund Olesen
e641c97670
Add RISC-V encodings for brz and brnz.
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These branches compare a register to zero. RISC-V implements this with
the %x0 hard-coded zero register.
2017-04-03 15:20:57 -07:00
Jakob Stoklund Olesen
479ff156c1
Add conditional branch encodings for RISC-V.
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Not all br_icmp opcodes are present in the ISA. The missing ones can be
reached by commuting operands.
Don't attempt to encode EBB offsets yet. For now just emit an EBB
relocation for the branch instruction.
2017-04-03 15:16:25 -07:00
Jakob Stoklund Olesen
0530e822d4
Add RISC-V encodings for lui.
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This instruction can materialize constants with the low 12 bits clear.
2017-04-03 12:27:22 -07:00
Jakob Stoklund Olesen
4e398164d2
Add icmp_imm encodings for RISC-V.
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The ISA has icmp_imm slt/ult with 12-bit signed immediate operands.
2017-04-03 10:59:28 -07:00
Jakob Stoklund Olesen
e9907fbdd6
Add RISC-V encodings for supported icmp variants.
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Only slt and ult variants are in the instruction set. Other condition
codes must be synthesized.
2017-03-31 13:47:07 -07:00
Jakob Stoklund Olesen
377550b835
Add return_reg encodings for RISC-V.
2017-02-21 16:29:23 -08:00
Jakob Stoklund Olesen
0b9b956695
Split out instruction definitions.
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- cdsl.instructions defines the Instruction class.
- base.instructions defines the base instruction set.
2016-11-08 12:33:50 -08:00
Jakob Stoklund Olesen
af6355e2ef
Move the 'meta' dir to 'lib/cretonne/meta'.
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The 'lib/cretonne' directory will be the new root of a stand-alone
cretonne crate containg both Python and Rust sources.
This is in preparation for publishing crates on crates.io.
2016-10-17 14:19:23 -07:00
