When an instruction doesn't have a valid encoding for the target ISA, it
needs to be legalized. Different legalization strategies can be
expressed as separate XFormGroup objects.
Make the choice of XFormGroup configurable per CPU mode, rather than
depending on a hard-coded default.
Add a CPUMode.legalize_type() method which assigns an XFormGroup to
controlling type variables and lets you set a default.
Add a `legalize` field to Level1Entry so the first-level hash table
lookup gives us the configured default legalization action for the
instruction's controlling type variable.
The encoding tables contain references to numbered ISA predicates.
- Give the ISA Flags types a predicate_view() method which returns a
PredicateView.
- Delete the old predicate_bytes() method which returned a raw &[u8].
- Use a 'static lifetime for the encoding list slice in the Encodings
iterator, and a single 'a lifetime for everything else.
ARM has all of these as scalar integer instructions. Intel has band_not
in SSE and as a scalar in BMI1.
Add the trivial legalization patterns that use a bnot instruction.
These map to single Intel instructions.
The i64 to float conversions are not tested yet. The encoding tables
can't yet differentiate instructions on a secondary type variable alone.
This instruction returns a `b1` value which is represented as the output
of a setCC instruction which is the low 8 bits of a GPR register. Use a
cmp+setCC macro recipe to encode this. That is not ideal, but we can't
represent CPU flags yet.
A fallthrough jump is actually represented as 0 bytes, so no encoding is
needed.
Also allow for unencoded instructions in the generated emit_inst
implementations. The verifier has stricter rules for when this is
allowed.
Register locations can change throughout an EBB. Make sure the
emit_inst() function considers this when encoding instructions and
update the register diversion tracker.
Add instructions representing Intel's division instructions which use a
numerator that is twice as wide as the denominator and produce both the
quotient and remainder.
Add encodings for the x86_[su]divmodx instructions.
This function will emit the binary machine code into contiguous raw
memory while sending relocations to a RelocSink.
Add a MemoryCodeSink for generating machine code directly into memory
efficiently. Allow the TargetIsa to provide emit_function
implementations that are specialized to the MemoryCodeSink type to avoid
needless small virtual callbacks to put1() et etc.
Fixes#11.
Presets are groups of settings and values applied at once. This is used
as a shorthand in test files, so for example "isa intel nehalem" enables
all of the CPUID bits that the Nehalem micro-architecture provides.
Change the result type for the bit-counting instructions from a fixed i8
to the iB type variable which is the type of the input. This matches the
convention in WebAssembly, and at least Intel's instructions will set a
full register's worth of count result, even if it is always < 64.
Duplicate the Intel 'ur' encoding recipe into 'umr' and 'urm' variants
corresponding to the RM and MR encoding variants. The difference is
which register is encoded as 'reg' and which is 'r/m' in the ModR/M
byte. A 'mov' register copy uses the MR variant, a unary popcnt uses the
RM variant.
This is the main entry point to the code generator. It returns the
computed size of the functions code.
Also add a 'test compile' command which runs the whole code generation
pipeline.
We allow ghost instructions to exist if they have no side effects.
Instructions that affect control flow or that have other side effects
must be encoded.
Teach the IL verifier to enforce this. Once any instruction has an
encoding, all instructions with side effects must have an encoding.
* Reduce code duplication in TypeConstraint subclasses; Add ConstrainWiderOrEqual to ti and to ireduce,{s,u}extend and f{promote,demote}; Fix bug in emitting constraint edges in TypeEnv.dot(); Modify runtime constraint checks to reject match when they encounter overflow
* Rename Constrain types to something shorter; Move lane_bits/lane_counts in subclasses of ValueType; Add wider_or_eq function in rust and python;
* API and data structures proposal for the SSA construction module
* Polished API and implemented trivial functions
* API more explicit, Variable now struct parameter
* Sample test written to see how the API could be used
* Implemented local value numbering for SSABuilder
* Implemented SSA within a single Ebb
* Unfinished unoptimized implementation for recursive use and seal
* Working global value numbering
The SSABuilder now create ebb args and modifies jump instructions accordingly
* Updated doc and improved branch argument modifying.
Removed instructions::branch_arguments and instructions::branch_argument_mut
* SSA building: bugfix, asserts and new test case
Missing a key optimization to remove cycles of Phi
* SSA Building: small changes after code review
Created helper function for seal_block (which now contains sanity checks)
* Optimization: removed useless phis (ebb arguments)
Using pessimistic assumption that when using a non-def variable in an unsealed block we create an ebb argument which is removed when sealing if we detect it as useless
Using aliases to avoid rewriting variables
* Changed the semantics of remove_ebb_arg and turned it into a proper API method
* Adapted ssa branch to changes in the DFG API
* Abandonned SparseMaps for EntityMaps, added named structure for headr block data.
* Created skeletton for a Cretonne IL builder frontend
* Frontend IL builder: first draft of implementation with example of instruction methods
* Working basic implementation of the frontend
Missing handling of function arguments and return values
* Interaction with function signature, sample test, more checks
* Test with function verifier, seal and fill sanity check
* Implemented python script to generate ILBuilder methods
* Added support for jump tables and stack slot
* Major API overhaul
* No longer generating rust through Python but implements InstBuilder
* No longer parametrized by user's blocks but use regular `Ebb`
* Reuse of allocated memory via distinction between ILBuilder and FunctionBuilder
* Integrate changes from StackSlot
* Improved error message
* Added support for jump arguments supplied by the user
* Added an ebb_args proxy method needed
* Adapted to Entity_ref splitted into a new module
* Better error messages and fixed tests
* Added method to change jump destination
* We whould be able to add unreachable code
* Added inst_result proxy to frontend
* Import support
* Added optimization for SSA construction:
If multiple predecessors but agree on value don't create EBB argument
* Move unsafe and not write-only funcs apart, improved doc
* Added proxy function for append_ebb_arg
* Support for unreachable code and better layout of the Ebbs
* Fixed a bug yielding an infinite loop in SSA construction
* SSA predecessors lookup code refactoring
* Fixed bug in unreachable definition
* New sanity check and display debug function
* Fixed bug in verifier and added is_pristine ;ethod for frontend
* Extended set of characters printable in function names
To be able to print names of functions in test suite
* Fixes and improvements of SSA construction after code review
* Bugfixes for frontend code simplification
* On-the-fly critical edge splitting in case of br_table with jump arguments
* No more dangling undefined values, now attached as EBB args
* Bugfix: only split corresponding edges on demand, not all br_table edges
* Added signature retrieval method
* Bugfix for critical edge splitting not sealing the ebbs it created
* Proper handling of SSA side effects by the frontend
* Code refactoring: moving frontend and SSA to new crate
* Frontend: small changes and bugfixes after code review
Add a TailRecipe.rex() method which creates an encoding recipe with a
REX prefix.
Define I64 encodings with REX.W for i64 operations and with/without REX
for i32 ops. Only test the with-REX encodings for now. We don't yet have
an instruction shrinking pass that can select the non-REX encodings.
Use a PUT_OP macro in the TailRecipe Python class to replace the code
snippet that emits the prefixes + opcode part of the instruction encoding.
Prepare for the addition of REX prefixes by giving the PUT_OP functions
a third argument representing the REX prefix. For the non-REX encodings,
verify that no REX bits wold be needed.
Generate code to:
- Unwrap the instruction and generate an error if the instruction format
doesn't match the recipe.
- Look up the value locations of register and stack arguments.
The recipe_* functions in the ISA binemit modules now take these
unwrapped items as arguments.
Also add an optional `emit` argument to the EncRecipe constructor which
makes it possible to provide inline Rust code snippets for code
emission. This requires a lot less boilerplate than recipe_* functions.
