yuyang-ok
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cdecc858b4
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add riscv64 backend for cranelift. (#4271)
Add a RISC-V 64 (`riscv64`, RV64GC) backend.
Co-authored-by: yuyang <756445638@qq.com>
Co-authored-by: Chris Fallin <chris@cfallin.org>
Co-authored-by: Afonso Bordado <afonsobordado@az8.co>
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2022-09-27 17:30:31 -07:00 |
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Anton Kirilov
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2ba4bce5cc
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Merge pull request from GHSA-7f6x-jwh5-m9r4
Copyright (c) 2022, Arm Limited.
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2022-07-20 11:53:56 -05:00 |
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Sam Parker
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e142f587a7
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[AArch64] Refactor ALUOp3 (#3950)
As well as adding generic pattern for msub along with runtests
for madd and msub.
Copyright (c) 2022, Arm Limited.
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2022-04-14 12:16:56 -07:00 |
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bjorn3
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a646f68553
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Remove legacy x86_64 backend tests
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2021-09-29 17:37:23 +02:00 |
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Afonso Bordado
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3f6b889067
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cranelift: Prevent panics when dividing INT_MIN / -1 in interpreter
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2021-08-24 09:27:54 -07:00 |
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Afonso Bordado
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a4770a7e28
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cranelift: Prevent overflow errors in interpreter for add,sub,mul
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2021-06-30 06:32:16 -07:00 |
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