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6792c062bf7d1b8964070888b66e7f18576cc46f
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1298 Commits

Author SHA1 Message Date
Nicolas B. Pierron
6792c062bf Add basic-blocks feature flag at the top-level Cargo.toml. 2019-07-25 14:27:44 +02:00
Sean Stangl
70c91f913d Produce more helpful basic block errors in cranelift-frontend. 
Previously, the error just notified that there was a failure.
The new-style error says specifically in which ebb, on which instruction.
 2019-07-23 07:58:57 -06:00
Sean Stangl
926e4c8bf8 Generate basic blocks for Wasm br_if. 2019-07-23 07:58:57 -06:00
Sean Stangl
ffa9d315e6 Add some comments to the frontend code. 2019-07-23 07:58:57 -06:00
Sean Stangl
5d1deecbb4 Give cranelift-wasm a "basic-blocks" feature. 2019-07-23 07:58:57 -06:00
Dan Gohman
4641fdd302 Bump version to 0.36.0 2019-07-19 16:28:40 -07:00
Artur Jamro
7a72ffefdd Add serde derive to PrimaryMap 2019-07-19 15:56:29 -07:00
Sean Stangl
8efaeec502 Verify that FunctionBuilder blocks are basic blocks in debug mode (#857) 
To use, enable the "basic-blocks" feature on cranelift-frontend.
 2019-07-19 09:52:05 -06:00
Sean Stangl
9b97ddf29a Enable basic block checks through a feature. (#856) 
This allows prefixing BB-specific code with "#[cfg(feature = "basic-blocks")]",
which avoids having to reference an environment variable across the codebase.

The easiest way to enable the feature locally is to add the arguments
'features = ["basic-blocks"]' to the workspace Cargo.toml, where it defines
the cranelift-codegen dependency.
 2019-07-18 09:59:28 -06:00
Andrew Brown
084e279def Add x86 implementation of splat instruction 2019-07-16 17:07:44 -07:00
Andrew Brown
3b36a1d1d8 Add x86 implementation of insertlane instruction 2019-07-16 17:07:44 -07:00
Andrew Brown
683e7c75a3 Add x86-specific shuffle instructions 
This includes both PSHUFD and PSHUFB; these are necessary to legalize future SIMD instructions.
 2019-07-16 17:07:44 -07:00
Andrew Brown
61772e9775 Add raw_bitcast instruction 
Casts bits as a different type of the same width with no change to the data (unlike bitcast)
 2019-07-16 17:07:44 -07:00
Andrew Brown
5f0e5567c1 Add scalar_to_vector instruction 
Moves scalar values in a GPR register to an FPR register
 2019-07-16 17:07:44 -07:00
Andrew Brown
356e6dafe2 Allow CDSL instructions to bind to vector types 2019-07-16 17:07:44 -07:00
Andrew Brown
c39a9b4e3f Assign vector arguments to FPR registers 2019-07-16 17:07:44 -07:00
Andrew Brown
659725b465 Add x86-specific SIMD settings, e.g. SSE2 
Also, ties SIMD ISA predicates to the shared enable_simd setting
 2019-07-16 17:07:44 -07:00
Andrew Brown
f2c48009e8 Disable SIMD features by default 2019-07-16 17:07:44 -07:00
Andrew Brown
8378297f33 Prepare legalizer codegen for SIMD features 
Contains fixes from @bnjbvr to codegen as a part of https://github.com/bnjbvr/cranelift/pull/2; necessary for SIMD features to work
 2019-07-16 17:07:44 -07:00
Dan Gohman
67dd0b5015 Bump version to 0.35.0 2019-07-12 15:48:19 -07:00
Artur Jamro
a64ada7e30 Do not import libc on windows (#848) 
* Do not import libc on windows
 2019-07-12 15:41:59 -07:00
Artur Jamro
9e884b4433 Add support for some serde serialization (#847) 
* Add support for some serde serialization
 2019-07-12 15:30:50 -07:00
Nicolas B. Pierron
8edc40cb49 BB-like manual legalization for x86 ISA 2019-07-12 14:20:26 +02:00
Mark McCaskey
f856b124fd Use Default trait for Position and DisplayFunctionAnnotations (#843) 2019-07-12 11:21:00 +02:00
Benson Chau
6a19866da2 issue #772: added an memmap replacement to support selinux 2019-07-11 18:16:41 -07:00
Benjamin Bouvier
bfc1468688 [docs] Don't accidentally generate doc tests; 2019-07-11 11:48:45 +02:00
Benjamin Bouvier
062ed8f6ea [docs] Remove rst annotations in instructions doc comments; 2019-07-11 11:48:45 +02:00
Benjamin Bouvier
abc3397017 [docs] Remove special handling of CDSL python modules; 2019-07-11 11:48:45 +02:00
Benjamin Bouvier
55f36ce81a [docs] Update docs to point to the docs.rs website; 2019-07-11 11:48:45 +02:00
Benjamin Bouvier
d5b80b2803 [meta] Generate full documentation for instructions in InstBuilder; 2019-07-11 11:48:45 +02:00
Benjamin Bouvier
84a6795873 [meta] Riscv: add back stacknull encodings for copy_nop; 2019-07-10 17:51:09 +02:00
Dan Gohman
59f6c81e4f Bump version to 0.34.0 2019-07-09 12:31:58 -07:00
Benjamin Bouvier
41a3d88b37 Fixes #837: Use an u64 comparison instead of a usize comparison in meta; 2019-07-09 18:15:30 +02:00
Sean Stangl
237d48477a Fix an outdated comment referring to FunctionLayout instead of Layout 2019-07-09 18:05:36 +02:00
Nicolas B. Pierron
3ac7466cab Legalize br_table to a BB-like format. 2019-07-09 16:48:54 +02:00
Nicolas B. Pierron
1963c223b1 Legalize trapz/trapnz to a BB-like format. 2019-07-09 16:02:49 +02:00
Benjamin Bouvier
f11fc34066 Build fix: add crates::predicates to the Riscv enc_tables file; 2019-07-09 11:31:21 +02:00
Benjamin Bouvier
56f6908020 [meta] Legalization: Don't generate a variable for replaced instructions; 
(since they're unused)
 2019-07-09 10:56:50 +02:00
Benjamin Bouvier
cd4c28ad97 [meta] Legalization: Unprefix some module paths to make code neater; 2019-07-09 10:56:50 +02:00
Benjamin Bouvier
15d8b95e72 [meta] Legalization: remove spurious Option wrapping for type variables; 2019-07-09 10:56:50 +02:00
Benjamin Bouvier
f1222dce10 [meta] Legalization: emit typeof type variables for results in all the cases; 2019-07-09 10:56:50 +02:00
Benjamin Bouvier
3545363006 Add ir::Types::lane_of as an alias of lane_type to be used in typevar constraints; 2019-07-09 10:56:50 +02:00
Benjamin Bouvier
4fef03f5f8 [meta] Legalization: remove spurious assert; 
This assert was added when porting legalization from Python to Rust and
doesn't hold when we have derived type variables.
 2019-07-09 10:56:50 +02:00
superriva
5672cd651c Fix mem::uninitialized depricated since 1.38 
Fix for `https://github.com/CraneStation/cranelift/issues/826`.
This fix will require 1.36 minimal version for all Cranelift. Right?

Update cranelift-simplejit/src/memory.rs

Co-Authored-By: bjorn3 <bjorn3@users.noreply.github.com>

Update memory.rs
 2019-07-08 15:21:56 +02:00
Nicolas B. Pierron
f431465802 Replace newly inserted fallthrough by jump. 2019-07-08 15:17:49 +02:00
Nicolas B. Pierron
8bfdfbe68b Use BB-like EBB in filetests/regalloc/*.clif 2019-07-08 15:17:49 +02:00
Nicolas B. Pierron
a1a4b9bfb1 Use BB-like EBB in filetests/verifier/*.clif 2019-07-08 15:17:49 +02:00
Nicolas B. Pierron
8c65ec0dde Use BB-like EBB in filetests/regress/*.clif 2019-07-08 15:17:49 +02:00
Nicolas B. Pierron
3c6ca9049e Use BB-like EBB in filetests/simple_gvn/*.clif 2019-07-08 15:17:49 +02:00
Nicolas B. Pierron
560619f749 Use BB-like EBB in filetests/cfg/*.clif 2019-07-08 15:17:49 +02:00