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65e6de234437b54c1f13697aa2c817acc2c6ef7a
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31 Commits

Author SHA1 Message Date
Andrew Brown
65e6de2344 Replace x86_packss with snarrow 
Since the Wasm specification contains narrowing instructions (see https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#integer-to-integer-narrowing) that lower to PACKSS*, the x86-specific instruction is not necessary in the CLIF IR.
 2020-07-02 09:35:45 -07:00
Andrew Brown
772ce73f7f Add x86_pblendw instruction 
This instruction is necessary for lowering `fcvt_from_uint`.
 2020-06-12 15:06:22 -07:00
Andrew Brown
546fc9ddf1 Add x86_vcvtudq2ps instruction 
This instruction converts i32x4 to f32x4 in several AVX512 feature sets.
 2020-06-12 15:06:22 -07:00
Andrew Brown
df171f01b5 Add x86_pmuludq 
This instruction multiplies the lower 32 bits of two 64x2 unsigned integers into an i64x2; this is necessary for lowering Wasm's i64x2.mul.
 2020-06-03 16:27:57 -07:00
Andrew Brown
9ba9fd0f64 Add x86-specific instruction for i64x2 multiplication 
Without this special instruction, legalizing to the AVX512 instruction AND the SSE instruction sequence is impossible. This extra instruction would be rendered unnecessary by the x64 backend.
 2020-06-03 16:27:57 -07:00
Andrew Brown
a27a079d65 Replace ExtractLane format with BinaryImm8 
Like https://github.com/bytecodealliance/wasmtime/pull/1762, this change the name of the `ExtractLane` format to the more-general `BinaryImm8` and renames its immediate argument from `lane` to `imm`.
 2020-05-29 19:56:27 -07:00
Andrew Brown
7d6e94b952 Replace InsertLane format with TernaryImm8 
The InsertLane format has an ordering (`value().imm().value()`) and immediate name (`"lane"`) that make it awkward to use for other instructions. This changes the ordering (`value().value().imm()`) and uses the default name (`"imm"`) throughout the codebase.
 2020-05-29 19:56:27 -07:00
Andrew Brown
fb6e8f784d Add x86 pack instructions 2020-04-23 10:55:54 -07:00
Andrew Brown
f5fc09f64a Add x86 unpack instructions 2020-04-23 10:55:54 -07:00
Benjamin Bouvier
1d5a678124 Fixes #1240: Add a new accessor to indicate that an opcode requires spilling all registers; 2020-03-23 12:19:28 +01:00
bjorn3
0a1bb3ba6c Add TLS support for ELF and MachO (#1174) 
* Add TLS support
* Add binemit and legalize tests
* Spill all caller-saved registers when necessary
 2020-02-25 17:50:04 -08:00
Andrew Brown
0ab5760fd7 Add x86 SIMD instructions for min and max 
Only the I8, I16, and I32 versions are included since Cranelift lacks support for AVX.
 2019-11-05 16:42:34 -08:00
Benjamin Bouvier
4632d35196 [meta] Remove the OperandBuilder, replace it with Operand ctors; 2019-10-30 18:39:20 +01:00
Peter Huene
9f506692c2 Fix clippy warnings. 
This commit fixes the current set of (stable) clippy warnings in the repo.
 2019-10-24 17:20:12 -07:00
Andrew Brown
186effc420 Add x86 SIMD vany_true and x86_ptest 
In order to implement SIMD's any_true (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#any-lane-true), we must legalize some instruction (I chose `vany_true`) to a sequence of `PTEST` and `SETNZ`. To emit `PTEST` I added the new CLIF instruction `x86_ptest` and used CLIF's `trueif ne` for `SETNZ`.
 2019-10-22 11:01:05 -07:00
Benjamin Bouvier
0243b642e3 [meta] Remove name lookups in formats; 
This does a lot at once, since there was no clear way to split the three
commits:

- Instruction need to be passed an explicit InstructionFormat,
- InstructionFormat deduplication is checked once all entities have been
defined;
 2019-10-22 14:05:12 +02:00
Benjamin Bouvier
d3e694fbe7 [meta] Remove unused InstructionGroup::{name, doc}; 2019-10-22 14:05:12 +02:00
Andrew Brown
f1904bffea Add x86 SIMD sshr and ushr 
Only the shifts with applicable SSE2 instructions are implemented here: PSRL* (for ushr) only has 16-64 bit instructions and PSRA* (for sshr) only has 16-32 bit instructions.
 2019-10-15 15:51:50 -07:00
Andrew Brown
6460fe705f Add x86 SIMD ishl 
Only the shifts with applicable SSE2 instructions (i.e. 16-64 bit width) are implemented here.
 2019-10-15 15:51:50 -07:00
Andrew Brown
295b2ef614 Avoid extra register movement when lowering an x86 insertlane to a float vector 2019-09-10 10:45:12 -07:00
Andrew Brown
00bedca274 Avoid extra register movement when lowering the x86 extractlane of a float vector 
This commit is based on the assumption that floats are already stored in XMM registers in x86. When extracting a lane, cranelift was moving the float to a regular register and back to an XMM register; this change avoids this by shuffling the float value to the lowest bits of the XMM register. It also assumes that the upper bits can be left as is (instead of zeroing them out).
 2019-09-10 10:45:12 -07:00
Benjamin Bouvier
d1d2e790b9 [meta] Morph a few pub into pub(crate), and remove dead code; 2019-09-06 15:47:20 +02:00
Benjamin Bouvier
29e3ec51c1 [meta] Introduce the Immediates structure instead of using dynamic lookup; 2019-09-06 15:47:20 +02:00
Andrew Brown
683e7c75a3 Add x86-specific shuffle instructions 
This includes both PSHUFD and PSHUFB; these are necessary to legalize future SIMD instructions.
 2019-07-16 17:07:44 -07:00
Benjamin Bouvier
062ed8f6ea [docs] Remove rst annotations in instructions doc comments; 2019-07-11 11:48:45 +02:00
Benjamin Bouvier
f1d1d1e960 [meta] Uniquely number every instruction in the Rust crate; 2019-07-03 18:39:28 +02:00
Benjamin Bouvier
70f79d23bf [meta] Make Builders build() instead of finish(); 2019-05-29 14:05:01 +02:00
Benjamin Bouvier
d9277f249b [meta] Introduce the InstructionGroupBuilder; 
This follows the rest of the code base data structures, where we have a
mutable data structure builder; once the data structure is constructed,
it's immutable.

This also makes the definition of instructions easier, and it paves the
way for defining immediate variants.
 2019-05-29 14:05:01 +02:00
Benjamin Bouvier
22a6823496 [meta] Rename cdsl/inst to cdsl/instructions; 2019-05-29 14:05:01 +02:00
Benjamin Bouvier
6053201128 [meta] Move the TypeSet building out of the TypeVar builder so as to test it; 2019-04-02 17:30:50 +02:00
Benjamin Bouvier
3c31eac48c [meta] Port Instruction/InstructionGroup to the Rust meta crate; 2019-03-28 14:13:29 +01:00