Commit Graph

1806 Commits

Author SHA1 Message Date
Benjamin Bouvier
19b5b0cc7b aarch64: pass a lowering context to gen_copy_reg_to_arg; 2020-04-24 17:41:14 +02:00
Benjamin Bouvier
0b13d8c848 aarch64: copy SP whenever it's involved in an address lowering with an explicit add; 2020-04-24 17:41:14 +02:00
Benjamin Bouvier
077556ac17 aarch64: correctly display fpu loads and stores; 2020-04-24 17:40:36 +02:00
Joey Gouly
f020f0812e arm64: Implement checks in division / remainder
This implements the divide by 0 and signed overflow checks that Wasm
specifies.

Copyright (c) 2020, Arm Limited.
2020-04-24 17:40:19 +02:00
Benjamin Bouvier
b6e6998713 aarch64: mask rotation counts and share code generation of left and right rotations;
Given an integer size N, a left rotation of K places is the same as a
right rotation of N - K places. This means we can use right rotations to
implement left rotations too.

The Cranelift's rotation semantics are inherited from WebAssembly, which
mean the rotation count is truncated modulo the operand's bit size. Note
the ROR aarch64 instruction has the same semantics, when both input
operands are registers.
2020-04-24 12:36:59 +02:00
Benjamin Bouvier
de92b7e014 aarch64: implement correct float-to-int conversion semantics;
These are inherited from wasm semantics.
2020-04-24 11:51:35 +02:00
Chris Fallin
8f462db645 Fix ImmLogic.invert(), and with it, fcopysign and float_misc test.
Previously, `fcopysign` was mysteriously failing to pass the
`float_misc` spec test. This was tracked down to bad logical-immediate
masks used to separate the sign and not-sign bits. In particular, the
masks for the and-not operations were wrong. The `invert()` function on
an `ImmLogic` immediate, it turns out, assumed every immediate would be
used by a 64-bit instruction; `ImmLogic` immediates are subtly different
for 32-bit instructions. This change tracks the instruction size (32 or
64 bits) intended for use with each such immediate, and passes it back
into `maybe_from_u64` when computing the inverted immediate.

Addresses several of the failures (`float_misc`, `f32_bitwise`) for
 #1521 (test failures) and presumably helps #1519 (SpiderMonkey
integration).
2020-04-23 13:06:13 -07:00
Andrew Brown
fb6e8f784d Add x86 pack instructions 2020-04-23 10:55:54 -07:00
Andrew Brown
341dc45cea Add DerivedFunction for splitting lane widths and doubling the number of lanes
Certain operations (e.g. x86_packss) will have operands with types like `NxM` but will return results with types like `(N/2)x(M*2)` (halve the lane width, double the number of lanes; maintain the same number of vector bits). This is equivalent to applying two `DerivedFunction`s to the type: `DerivedFunction::HalfWidth` then `DerivedFunction::DoubleVector`. Since there is no easy way to apply multiple `DerivedFunction`s (e.g. most of the logic is one-level deep, 1d5a678124/cranelift/codegen/meta/src/gen_inst.rs (L618-L621)), I added `DerivedFunction::SplitLanes` to do the necessary type conversion.
2020-04-23 10:55:54 -07:00
Andrew Brown
f5fc09f64a Add x86 unpack instructions 2020-04-23 10:55:54 -07:00
Andrew Brown
5f0286696c Add x86 implentation of 8x16 ishl
This involves some large mask tables that may hurt code size but reduce the number of instructions. See https://github.com/WebAssembly/simd/issues/117 for a more in-depth discussion on this.
2020-04-23 10:55:54 -07:00
Chris Fallin
2f1a2f4225 Merge pull request #1571 from cfallin/fix-aarch64-heap-oob
Fix aarch64 load trap info: HeapOutOfBounds, not OutOfBounds.
2020-04-22 12:15:32 -07:00
Benjamin Bouvier
65ef26b989 Add a setting to choose a register allocator algorithm to use with MachBackend; 2020-04-22 14:47:18 +02:00
Chris Fallin
dacadc8a34 Fix aarch64 load trap info: HeapOutOfBounds, not OutOfBounds.
This halfway solves a test failure: when temporarily disabling another
assert that is triggered by lack of debug info, this causes the
`custom_trap_handler` test to pass.
2020-04-21 15:30:58 -07:00
Alex Crichton
c9a0ba81a0 Implement interrupting wasm code, reimplement stack overflow (#1490)
* Implement interrupting wasm code, reimplement stack overflow

This commit is a relatively large change for wasmtime with two main
goals:

* Primarily this enables interrupting executing wasm code with a trap,
  preventing infinite loops in wasm code. Note that resumption of the
  wasm code is not a goal of this commit.

* Additionally this commit reimplements how we handle stack overflow to
  ensure that host functions always have a reasonable amount of stack to
  run on. This fixes an issue where we might longjmp out of a host
  function, skipping destructors.

Lots of various odds and ends end up falling out in this commit once the
two goals above were implemented. The strategy for implementing this was
also lifted from Spidermonkey and existing functionality inside of
Cranelift. I've tried to write up thorough documentation of how this all
works in `crates/environ/src/cranelift.rs` where gnarly-ish bits are.

A brief summary of how this works is that each function and each loop
header now checks to see if they're interrupted. Interrupts and the
stack overflow check are actually folded into one now, where function
headers check to see if they've run out of stack and the sentinel value
used to indicate an interrupt, checked in loop headers, tricks functions
into thinking they're out of stack. An interrupt is basically just
writing a value to a location which is read by JIT code.

When interrupts are delivered and what triggers them has been left up to
embedders of the `wasmtime` crate. The `wasmtime::Store` type has a
method to acquire an `InterruptHandle`, where `InterruptHandle` is a
`Send` and `Sync` type which can travel to other threads (or perhaps
even a signal handler) to get notified from. It's intended that this
provides a good degree of flexibility when interrupting wasm code. Note
though that this does have a large caveat where interrupts don't work
when you're interrupting host code, so if you've got a host import
blocking for a long time an interrupt won't actually be received until
the wasm starts running again.

Some fallout included from this change is:

* Unix signal handlers are no longer registered with `SA_ONSTACK`.
  Instead they run on the native stack the thread was already using.
  This is possible since stack overflow isn't handled by hitting the
  guard page, but rather it's explicitly checked for in wasm now. Native
  stack overflow will continue to abort the process as usual.

* Unix sigaltstack management is now no longer necessary since we don't
  use it any more.

* Windows no longer has any need to reset guard pages since we no longer
  try to recover from faults on guard pages.

* On all targets probestack intrinsics are disabled since we use a
  different mechanism for catching stack overflow.

* The C API has been updated with interrupts handles. An example has
  also been added which shows off how to interrupt a module.

Closes #139
Closes #860
Closes #900

* Update comment about magical interrupt value

* Store stack limit as a global value, not a closure

* Run rustfmt

* Handle review comments

* Add a comment about SA_ONSTACK

* Use `usize` for type of `INTERRUPTED`

* Parse human-readable durations

* Bring back sigaltstack handling

Allows libstd to print out stack overflow on failure still.

* Add parsing and emission of stack limit-via-preamble

* Fix new example for new apis

* Fix host segfault test in release mode

* Fix new doc example
2020-04-21 11:03:28 -07:00
Chris Fallin
7b24ff15db Merge pull request #1538 from bnjbvr/all-ones-unpatched
implement emit_all_ones_funcaddrs in new backend
2020-04-21 09:51:17 -07:00
Chris Fallin
d88098744b Merge pull request #1527 from cfallin/aarch64-fp-vcode-test
Add vcode test for floating-point, and fix two FP bugs.
2020-04-21 09:35:23 -07:00
Benjamin Bouvier
1323bb5a37 aarch64: correctly pass f32/f64 stack arguments in function calls; 2020-04-21 17:58:33 +02:00
Benjamin Bouvier
a7ca37e493 Honour the emit_all_ones_funcaddrs() settings when creating unpatched locations; 2020-04-21 17:22:53 +02:00
Chris Fallin
297d64b2c0 Merge pull request #1530 from bnjbvr/bbouvier-arm64-fixes
Pending arm64 fixes for Spidermonkey integration
2020-04-21 08:08:09 -07:00
Joey Gouly
ad9be0d445 arm64: Support bool constants
Copyright (c) 2020, Arm Limited.
2020-04-21 12:24:57 +02:00
Joey Gouly
3638f8a764 arm64: Add support for CCmp
Also add a test for SUBS/ADDS with XZR, as CMP/CMN are aliases.

Copyright (c) 2020, Arm Limited.
2020-04-21 12:19:07 +02:00
Benjamin Bouvier
d50e956974 Remove an unnecessary mutable qualifier when passing a function to compile; 2020-04-21 12:12:56 +02:00
Benjamin Bouvier
5b8b75def0 Baldrdash: implement support for sign-extension in returns; 2020-04-21 12:12:56 +02:00
Benjamin Bouvier
241c164e25 Implement pinned register usage through set_pinned_reg/get_pinned_reg; 2020-04-21 12:12:56 +02:00
Benjamin Bouvier
d1b5df31fd Baldrdash: use the right frame offset when loading arguments from the stack 2020-04-21 12:12:56 +02:00
Benjamin Bouvier
359dc76ae4 Baldrdash: callee-saved are only JIT callee-saved, not "JIT or natives".
And don't mark SP as callee-preserved (it's implicitly preserved);
2020-04-21 11:26:14 +02:00
Chris Fallin
c67fdca60c Change from review comments: fix comment.
Co-Authored-By: bjorn3 <bjorn3@users.noreply.github.com>
2020-04-20 11:19:13 -07:00
bjorn3
cb1c9ef085 Fix printing of LoadAddr 2020-04-18 13:24:06 +02:00
bjorn3
259de864e4 Reuse rd as tmp reg in LoadAddr 2020-04-18 13:24:06 +02:00
bjorn3
1bee1af755 Implement stack_addr for AArch64 2020-04-18 13:24:06 +02:00
Chris Fallin
5e53482a13 arm64: Support less-than-64-bit integers in Bitrev, Clz, Cls, and Popcnt instructions.
Includes a temporary bugfix for popcnt with 32-bit operand. The popcnt
issue was initially identified by Benjamin Bouvier <public@benj.me>, and
the root cause was debugged by Joey Gouly <joey.gouly@arm.com>. This
patch is simply a quick fix that zero-extends the operand to 64 bits;
Joey plans to contribute a more permanent fix shortly (tracked in
 #1537).
2020-04-17 16:42:46 -07:00
Alex Crichton
4c82da440a Move most wasmtime tests into one test suite (#1544)
* Move most wasmtime tests into one test suite

This commit moves most wasmtime tests into a single test suite which
gets compiled into one executable instead of having lots of test
executables. The goal here is to reduce disk space on CI, and this
should be achieved by having fewer executables which means fewer copies
of `libwasmtime.rlib` linked across binaries on the system. More
importantly though this means that DWARF debug information should only
be in one executable rather than duplicated across many.

* Share more build caches

Globally set `RUSTFLAGS` to `-Dwarnings` instead of individually so all
build steps share the same value.

* Allow some dead code in cranelift-codegen

Prevents having to fix all warnings for all possible feature
combinations, only the main ones which come up.

* Update some debug file paths
2020-04-17 17:22:12 -05:00
Andrew Brown
3159f0a76e Add unimplemented! arm for ConstAddr in Aarch64 (#1548) 2020-04-17 15:03:28 -05:00
Andrew Brown
3f47291f2e Add x86 implentation of 8x16 ushr
This involves some large mask tables that may hurt code size but reduce the number of instructions. See https://github.com/WebAssembly/simd/issues/117 for a more in-depth discussion on this.
2020-04-17 11:59:47 -07:00
Andrew Brown
fa35d88878 Verify that constant values are the correct size
Since we now allow constants of any size, we have to verify that `vconst` (currently the only user of the constant pool) is accessing constants that match its controlling type.
2020-04-17 11:59:47 -07:00
Andrew Brown
0672d1dc0f Declare constants in the function preamble
This allows us to give names to constants in the constant pool and then use these names in the function body. The original behavior, specifiying the constant value as an instruction immediate, is still supported as a shortcut but some filetests had to change since the canonical way of printing the CLIF constants is now in the preamble.
2020-04-17 11:59:47 -07:00
Chris Fallin
2b68abed6a Add vcode test for floating-point, and fix two FP bugs.
- Added a filetest for the vcode output of lowering every handled FP opcode.

- Fixed two bugs that were discovered while going through the lowerings:
  - Saturating FP->int operators would return `u{32,64}::MIN` rather than
    `0` for a NaN input.
  - `fcopysign` did not mask off the sign bit of the value whose sign is
    overwritten.

These probably would have been caught by Wasm conformance tests soon
(and the validity of these lowerings will ultimately be tested this way)
but let's get them right by inspection, too!
2020-04-16 13:43:52 -07:00
Peter Huene
2fb7e9f3c2 Return error for register mapping failure.
This commit removes a panic when a register mapping fails and instead returns
an error from creating the unwind information.
2020-04-16 11:15:35 -07:00
Peter Huene
09a3f10a48 Move UnwindInfo definition out of x86 ABI.
This commit moves the opaque definition of Windows x64 UnwindInfo out of the
ISA and into a location that can be easily used by the top level `UnwindInfo`
enum.

This allows the `unwind` feature to be independent of the individual ISAs
supported.
2020-04-16 11:15:34 -07:00
Peter Huene
f7e9f86ba9 Refactor unwind generation in Cranelift.
This commit makes the following changes to unwind information generation in
Cranelift:

* Remove frame layout change implementation in favor of processing the prologue
  and epilogue instructions when unwind information is requested.  This also
  means this work is no longer performed for Windows, which didn't utilize it.
  It also helps simplify the prologue and epilogue generation code.

* Remove the unwind sink implementation that required each unwind information
  to be represented in final form. For FDEs, this meant writing a
  complete frame table per function, which wastes 20 bytes or so for each
  function with duplicate CIEs.  This also enables Cranelift users to collect the
  unwind information and write it as a single frame table.

* For System V calling convention, the unwind information is no longer stored
  in code memory (it's only a requirement for Windows ABI to do so).  This allows
  for more compact code memory for modules with a lot of functions.

* Deletes some duplicate code relating to frame table generation.  Users can
  now simply use gimli to create a frame table from each function's unwind
  information.

Fixes #1181.
2020-04-16 11:15:32 -07:00
Chris Fallin
7da6101732 Merge pull request #1494 from cfallin/arm64-merge
Add new `MachInst` backend and ARM64 support.
2020-04-16 10:02:02 -07:00
Chris Fallin
48cf2c2f50 Address review comments:
- Undo temporary changes to default features (`all-arch`) and a
  signal-handler test.
- Remove `SIGTRAP` handler: no longer needed now that we've found an
  "undefined opcode" option on ARM64.
- Rename pp.rs to pretty_print.rs in machinst/.
- Only use empty stack-probe on non-x86. As per a comment in
  rust-lang/compiler-builtins [1], LLVM only supports stack probes on
  x86 and x86-64. Thus, on any other CPU architecture, we cannot refer
  to `__rust_probestack`, because it does not exist.
- Rename arm64 to aarch64.
- Use `target` directive in vcode filetests.
- Run the flags verifier, but without encinfo, when using new backends.
- Clean up warning overrides.
- Fix up use of casts: use u32::from(x) and siblings when possible,
  u32::try_from(x).unwrap() when not, to avoid silent truncation.
- Take immutable `Function` borrows as input; we don't actually
  mutate the input IR.
- Lots of other miscellaneous cleanups.

[1] cae3e6ea23/src/probestack.rs (L39)
2020-04-15 17:21:28 -07:00
Samrat Man Singh
4d34c22a1c Use F64X2 as type when saving and restoring XMM registers
When adding floating-point registers as callee-saved register to
block- and function parameter lists add them as `F64X2` arguments.
2020-04-13 09:48:08 -07:00
Chris Fallin
60990aeaae ARM64 backend, part 8 / 11: integration.
This patch ties together the new backend infrastructure with the
existing Cranelift codegen APIs.

With all patches in this series up to this patch applied, the ARM64
compiler is now functional and can be used. Two uses of this
functionality -- filecheck-based tests and integration into wasmtime --
will come in subsequent patches.
2020-04-11 17:52:37 -07:00
Chris Fallin
a0e629ecfb ARM64 backend, part 7 / 11: Arm64Backend toplevel.
This patch ties together the previously-committed pieces to implement
the `MachBackend` trait for ARM64.
2020-04-11 17:52:29 -07:00
Chris Fallin
aaa5a127c8 ARM64 backend, part 6 / 11: CLIF -> VCode<Inst> lowering.
This patch adds the lowering implementation that translates Cranelift IR
(CLIF) function bodies to VCode<Inst>, i.e., ARM64 machine instructions.

This patch contains code written by Julian Seward <jseward@acm.org> and
Benjamin Bouvier <public@benj.me>, originally developed on a side-branch
before rebasing and condensing into this patch series. See the `arm64`
branch at `https://github.com/cfallin/wasmtime` for original development
history.

This patch also contains code written by Joey Gouly
<joey.gouly@arm.com> and contributed to the above branch. These
contributions are "Copyright (c) 2020, Arm Limited."

Co-authored-by: Julian Seward <jseward@acm.org>
Co-authored-by: Benjamin Bouvier <public@benj.me>
Co-authored-by: Joey Gouly <joey.gouly@arm.com>
2020-04-11 17:52:21 -07:00
Chris Fallin
0f725a3c5c ARM64 backend, part 5 / 11: ABI implementation.
This patch provides an ARM64 implementation of the ABI-related traits
required by the new backend infrasturcture. It will be used by the
lowering code, when that is in place in a subsequent patch.

This patch contains code written by Julian Seward <jseward@acm.org> and
Benjamin Bouvier <public@benj.me>, originally developed on a side-branch
before rebasing and condensing into this patch series. See the `arm64`
branch at `https://github.com/cfallin/wasmtime` for original development
history.

This patch also contains code written by Joey Gouly
<joey.gouly@arm.com> and contributed to the above branch. These
contributions are "Copyright (c) 2020, Arm Limited."

Co-authored-by: Julian Seward <jseward@acm.org>
Co-authored-by: Benjamin Bouvier <public@benj.me>
Co-authored-by: Joey Gouly <joey.gouly@arm.com>
2020-04-11 17:52:11 -07:00
Chris Fallin
548ce947bf ARM64 backend, part 4 / 11: ARM64 instruction definitions.
This patch provides the bottom layer of the ARM64 backend: it defines
the `Inst` type, which represents a single machine instruction, and
defines emission routines to produce machine code from a `VCode`
container of `Insts`. The backend cannot produce `Inst`s with just this
patch; that will come with later parts.

This patch contains code written by Julian Seward <jseward@acm.org> and
Benjamin Bouvier <public@benj.me>, originally developed on a side-branch
before rebasing and condensing into this patch series. See the `arm64`
branch at `https://github.com/cfallin/wasmtime` for original development
history.

This patch also contains code written by Joey Gouly
<joey.gouly@arm.com> and contributed to the above branch. These
contributions are "Copyright (c) 2020, Arm Limited."

Finally, a contribution from Joey Gouly contains the following notice:

    This is a port of VIXL's Assembler::IsImmLogical.

    Arm has the original copyright on the VIXL code this was ported from
    and is relicensing it under Apache 2 for Cranelift.

Co-authored-by: Julian Seward <jseward@acm.org>
Co-authored-by: Benjamin Bouvier <public@benj.me>
Co-authored-by: Joey Gouly <joey.gouly@arm.com>
2020-04-11 17:51:45 -07:00
Chris Fallin
d83574261c ARM64 backend, part 3 / 11: MachInst infrastructure.
This patch adds the MachInst, or Machine Instruction, infrastructure.
This is the machine-independent portion of the new backend design. It
contains the implementation of the "vcode" (virtual-registerized code)
container, the top-level lowering algorithm and compilation pipeline,
and the trait definitions that the machine backends will fill in.

This backend infrastructure is included in the compilation of the
`codegen` crate, but it is not yet tied into the public APIs; that patch
will come last, after all the other pieces are filled in.

This patch contains code written by Julian Seward <jseward@acm.org> and
Benjamin Bouvier <public@benj.me>, originally developed on a side-branch
before rebasing and condensing into this patch series. See the `arm64`
branch at `https://github.com/cfallin/wasmtime` for original development
history.

Co-authored-by: Julian Seward <jseward@acm.org>
Co-authored-by: Benjamin Bouvier <public@benj.me>
2020-04-11 17:51:11 -07:00