Commit Graph

7 Commits

Author SHA1 Message Date
Dan Gohman
4e67e08efd Use the target-lexicon crate.
This switches from a custom list of architectures to use the
target-lexicon crate.

 - "set is_64bit=1; isa x86" is replaced with "target x86_64", and
   similar for other architectures, and the `is_64bit` flag is removed
   entirely.

 - The `is_compressed` flag is removed too; it's no longer being used to
   control REX prefixes on x86-64, ARM and Thumb are separate
   architectures in target-lexicon, and we can figure out how to
   select RISC-V compressed encodings when we're ready.
2018-05-30 06:13:35 -07:00
Dan Gohman
1c760ab179 Rename intel to x86.
x86 is the more accurate name, as there are non-Intel x86 implementations.

Fixes #263.
2018-04-12 10:02:16 -07:00
Jakob Stoklund Olesen
fdb97da21b Implement a poor man's jump table.
We will eventually support real jump tables, but for now just expand
br_table into a sequence of conditional branches.
2017-09-25 10:56:14 -07:00
Jakob Stoklund Olesen
e8723be33f Add trap codes to the Cretonne IL.
The trap and trapz/trapnz instructions now take a trap code immediate
operand which indicates the reason for trapping.
2017-09-20 15:50:02 -07:00
Jakob Stoklund Olesen
87c5f27ff7 Intel encodings for trap.
Use a ud2 instruction which generates an undefined instruction
exception.
2017-07-19 15:01:32 -07:00
Jakob Stoklund Olesen
c9bbc1e86e Don't require that the fallthrough instruction has an encoding.
A fallthrough jump is actually represented as 0 bytes, so no encoding is
needed.

Also allow for unencoded instructions in the generated emit_inst
implementations. The verifier has stricter rules for when this is
allowed.
2017-07-19 09:30:04 -07:00
Jakob Stoklund Olesen
efdbf0d735 Add Intel encodings for jump and branch instructions.
Just implement jump, brz, and brnz as needed for WebAssembly.
2017-07-19 09:15:19 -07:00