Commit Graph

3233 Commits

Author SHA1 Message Date
bjorn3
53ec12d519 Rustfmt 2021-09-29 16:27:47 +02:00
bjorn3
9e5201d88f Fix all dead-code warnings in cranelift-codegen 2021-09-29 16:27:47 +02:00
bjorn3
3e4167ba95 Remove registers from cranelift-codegen-meta 2021-09-29 16:27:47 +02:00
bjorn3
18bd27e90b Remove legalizer support from cranelift-codegen-meta 2021-09-29 16:27:45 +02:00
bjorn3
d499933612 Remove encoding generation from cranelift-codegen-meta 2021-09-29 16:23:58 +02:00
bjorn3
d8818c967e Fix all dead-code warnings in cranelift-codegen-meta 2021-09-29 16:23:58 +02:00
bjorn3
59e18b7d1b Remove the old riscv backend 2021-09-29 16:23:57 +02:00
bjorn3
9e34df33b9 Remove the old x86 backend 2021-09-29 16:13:46 +02:00
Alex Crichton
1ee2af0098 Remove the lightbeam backend (#3390)
This commit removes the Lightbeam backend from Wasmtime as per [RFC 14].
This backend hasn't received maintenance in quite some time, and as [RFC
14] indicates this doesn't meet the threshold for keeping the code
in-tree, so this commit removes it.

A fast "baseline" compiler may still be added in the future. The
addition of such a backend should be in line with [RFC 14], though, with
the principles we now have for stable releases of Wasmtime. I'll close
out Lightbeam-related issues once this is merged.

[RFC 14]: https://github.com/bytecodealliance/rfcs/pull/14
2021-09-27 12:27:19 -05:00
Chris Fallin
344a219245 Merge pull request #3383 from akirilov-arm/vany_true
Cranelift AArch64: Fix the VanyTrue implementation for 64-bit elements
2021-09-24 09:26:36 -07:00
Anton Kirilov
0fb3acfb94 Cranelift AArch64: Fix the VanyTrue implementation for 64-bit elements
Copyright (c) 2021, Arm Limited.
2021-09-23 20:39:46 +01:00
Anton Kirilov
930b1f17f0 Cranelift AArch64: Implement scalar FmaxPseudo and FminPseudo
Copyright (c) 2021, Arm Limited.
2021-09-23 15:11:01 +01:00
Chris Fallin
65fde3a86b Merge pull request #3380 from dheaton-arm/implement-iabs
Implement `Iabs` for the interpreter
2021-09-22 10:00:53 -07:00
Chris Fallin
b076c99af9 Merge pull request #3379 from dheaton-arm/implement-sqmulroundsat
Implement `SqmulRoundSat` for interpreter
2021-09-22 09:59:13 -07:00
Chris Fallin
dd7310df04 Merge pull request #3361 from dheaton-arm/implement-vecops
Implement `VhighBits` & `Vselect` for interpreter
2021-09-22 09:22:52 -07:00
Chris Fallin
76f9cfd79c Merge pull request #3354 from afonso360/interp-b
Add `bextend`,`breduce` and `bmask` to interpreter
2021-09-22 09:22:04 -07:00
Chris Fallin
3474965ca6 Merge pull request #3322 from sparker-arm/aarch64-lse-ops
AArch64 LSE atomic_rmw support
2021-09-22 09:21:28 -07:00
dheaton-arm
faaf6b537a Prevent running tests on legacy backend.
Copyright (c) 2021, Arm Limited
2021-09-22 13:50:31 +01:00
dheaton-arm
539b1de5f4 Prevent test running on legacy backend.
Copyright (c) 2021, Arm Limited
2021-09-22 13:48:59 +01:00
dheaton-arm
cb30ecc7bc Implement Iabs for the interpreter
Implemented `Iabs` to return the absolute integer value with wrapping.

Copyright (c) 2021, Arm Limited
2021-09-22 12:59:30 +01:00
dheaton-arm
02ff19f2fc Implement SqmulRoundSat for interpreter
Implemented `SqmulRoundSat` for the Cranelift interpreter, performing
QN-format fixed point multiplication for 16 and 32-bit integers in
SIMD vectors.

Copyright (c) 2021, Arm Limited
2021-09-22 12:58:41 +01:00
dheaton-arm
63d85e1dc3 Prevent running simd-vhighbits.clif on legacy backend.
Copyright (c) 2021, Arm Limited.
2021-09-22 11:43:57 +01:00
dheaton-arm
335177a97e Remove legacy backend from test
Copyright (c) 2021, Arm Limited
2021-09-22 09:42:18 +01:00
Afonso Bordado
9a95ce75f1 cranelift: Add bmask to interpreter 2021-09-21 18:43:53 +01:00
Afonso Bordado
3ee180420e cranelift: Add breduce tests to interpreter 2021-09-21 18:21:48 +01:00
Afonso Bordado
c7d595ae46 cranelift: Add bextend tests to interpreter 2021-09-21 18:21:48 +01:00
Chris Fallin
38728c5746 Merge pull request #3362 from dheaton-arm/implement-unarrow
Implement `Unarrow`, `Uunarrow`, and `Snarrow` for the interpreter
2021-09-21 10:06:46 -07:00
Chris Fallin
e0bd4bd007 Merge pull request #3363 from dheaton-arm/implement-widening-pairwise-dotprod
Implement `WideningPairwiseDotProductS` for interpreter
2021-09-21 10:05:07 -07:00
Chris Fallin
ebe2af6eaa Merge pull request #3351 from afonso360/parser-i128
cranelift: Add support for parsing i128 data values
2021-09-21 10:04:27 -07:00
Ulrich Weigand
51131a3acc Fix s390x regressions (#3330)
- Add relocation handling needed after PR #3275
- Fix incorrect handling of signed constants detected by PR #3056 test
- Fix LabelUse max pos/neg ranges; fix overflow in buffers.rs
- Disable fuzzing tests that require pre-built v8 binaries
- Disable cranelift test that depends on i128
- Temporarily disable memory64 tests
2021-09-20 09:12:36 -05:00
dheaton-arm
8abb19cbd8 Generate new_vec using an iterator chain
Copyright (c) 2021, Arm Limited
2021-09-20 10:31:34 +01:00
dheaton-arm
3fc29f5f6c Return u128 from bounds; form new_vec from iter chain
Copyright (c) 2021, Arm Limited
2021-09-20 09:57:19 +01:00
Afonso Bordado
3a4ebd7727 cranelift: Deduplicate match_imm functions
Transforming this into a generic function is proving to be a challenge
since most of the necessary methods are not in a trait. We also need to
cast between the signed and unsigned types, which is difficult to do
in a generic function.

This can be solved for example by adding the num crate as a dependency.
But adding a dependency just to solve this issue seems a bit much.
2021-09-19 15:03:46 +01:00
Afonso Bordado
eae1b2d246 cranelift: Update i128 tests to use i128 values in functions 2021-09-19 15:02:06 +01:00
Afonso Bordado
8115e7252d cranelift: Add support for i128 immediates in parser 2021-09-19 15:02:04 +01:00
Dan Gohman
47490b4383 Use rsix to make system calls in Wasmtime. (#3355)
* Use rsix to make system calls in Wasmtime.

`rsix` is a system call wrapper crate that we use in `wasi-common`,
which can provide the following advantages in the rest of Wasmtime:

 - It eliminates some `unsafe` blocks in Wasmtime's code. There's
   still an `unsafe` block in the library, but this way, the `unsafe`
   is factored out and clearly scoped.

 - And, it makes error handling more consistent, factoring out code for
   checking return values and `io::Error::last_os_error()`, and code that
   does `errno::set_errno(0)`.

This doesn't cover *all* system calls; `rsix` doesn't implement
signal-handling APIs, and this doesn't cover calls made through `std` or
crates like `userfaultfd`, `rand`, and `region`.
2021-09-17 15:28:56 -07:00
Chris Fallin
6a98fe2104 Merge pull request #3332 from afonso360/interp-icmp
cranelift: Add SIMD `icmp` to interpreter
2021-09-17 15:13:44 -07:00
Chris Fallin
c9834ee91c Merge pull request #3329 from uweigand/datavalue-endian-fix
cranelift: Fix big-endian regression in data_value.rs
2021-09-17 14:55:07 -07:00
Afonso Bordado
e17d9cfbab cranelift: Rename icmp type variable 2021-09-17 22:17:54 +01:00
Chris Fallin
1f2d1c097d Merge pull request #3364 from dheaton-arm/implement-smulhi
Implement `Smulhi` for interpreter
2021-09-17 12:56:37 -07:00
Chris Fallin
94151434ce Merge pull request #3357 from akirilov-arm/aarch64_emission_checks
Cranelift AArch64: Avoid invalid encodings for some vector instructions
2021-09-17 12:48:18 -07:00
Nick Fitzgerald
a1f4b46f64 Bump Wasmtime to version 0.30.0; cranelift to 0.77.0 2021-09-17 10:33:50 -07:00
Nick Fitzgerald
101998733b Merge pull request from GHSA-v4cp-h94r-m7xf
Fix a use-after-free bug when passing `ExternRef`s to Wasm
2021-09-17 10:27:29 -07:00
dheaton-arm
2f0ce4c86c Implement Smulhi for interpreter
Implemented `Smulhi` for the Cranelift interpreter, performing signed
integer multiplication and producing the high half of a double-length
result.

Copyright (c) 2021, Arm Limited
2021-09-17 16:49:38 +01:00
dheaton-arm
3b9bfc8187 Implement WideningPairwiseDotProductS for interpreter
Implemented `WideningPairwiseDotProductS` to perform sign-extending
length-doubling multiplication on corresponding elements from two
`i16x8` SIMD vectors, performing a pairwise add on the results (thus
returning `i32x4`).

Copyright (c) 2021, Arm Limited
2021-09-17 13:31:16 +01:00
dheaton-arm
83c3bc5b9d Implement Unarrow, Uunarrow, and Snarrow for the interpreter
Implemented the following Opcodes for the Cranelift interpreter:
- `Unarrow` to combine two SIMD vectors into a new vector with twice
the lanes but half the width, with signed inputs which are clamped to
`0x00`.
- `Uunarrow` to perform the same operation as `Unarrow` but treating
inputs as unsigned.
- `Snarrow` to perform the same operation as `Unarrow` but treating
both inputs and outputs as signed, and saturating accordingly.

Note that all 3 instructions saturate at the type boundaries.

Copyright (c) 2021, Arm Limited
2021-09-17 13:26:10 +01:00
dheaton-arm
224a4b4094 Implement VhighBits & Vselect for interpreter
Implemented the following Opcodes for the Cranelift interpreter:
- `VhighBits` to reduce a vector to a scalar integer formed by
concatenating the MSB of each lane.
- `Vselect` to select lanes from two vectors controlled by a boolean
vector.

Copyright (c) 2021, Arm Limited
2021-09-17 11:54:58 +01:00
Anton Kirilov
a8aec2e0e6 Cranelift AArch64: Avoid invalid encodings for some vector instructions
Copyright (c) 2021, Arm Limited.
2021-09-16 12:26:58 +01:00
Sam Parker
62a317773a added aarch64 has_lse targets to atomic-rmw run tests 2021-09-15 16:07:36 +01:00
Sam Parker
7da76f0601 cargo fmt 2021-09-15 16:01:51 +01:00