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479ff156c13384de0f94c00a25a3e817a3aa6091
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18 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
479ff156c1 Add conditional branch encodings for RISC-V. 
Not all br_icmp opcodes are present in the ISA. The missing ones can be
reached by commuting operands.

Don't attempt to encode EBB offsets yet. For now just emit an EBB
relocation for the branch instruction.
 2017-04-03 15:16:25 -07:00
Jakob Stoklund Olesen
0530e822d4 Add RISC-V encodings for lui. 
This instruction can materialize constants with the low 12 bits clear.
 2017-04-03 12:27:22 -07:00
Jakob Stoklund Olesen
4e398164d2 Add icmp_imm encodings for RISC-V. 
The ISA has icmp_imm slt/ult with 12-bit signed immediate operands.
 2017-04-03 10:59:28 -07:00
Jakob Stoklund Olesen
e9907fbdd6 Add RISC-V encodings for supported icmp variants. 
Only slt and ult variants are in the instruction set. Other condition
codes must be synthesized.
 2017-03-31 13:47:07 -07:00
Jakob Stoklund Olesen
910e4e6174 Coalesce some formats into MultiAry. 
Allow some flexibility in the signature matching for instruction
formats. In particular, look for a value list format as a second chance
option.

The Return, ReturnReg, and TernaryOverflow formats all fit the single
MultiAry catch-all format for instructions without immediate operands.
 2017-03-10 12:32:44 -08:00
Jakob Stoklund Olesen
377550b835 Add return_reg encodings for RISC-V. 2017-02-21 16:29:23 -08:00
Jakob Stoklund Olesen
2390e3e3f0 Add operand register constraints. 
Every encoding recipe must specify register constraints on input and
output values.

Generate recipe constraint tables along with the other encoding tables.
 2017-01-25 13:35:18 -08:00
Jakob Stoklund Olesen
1d21422032 Generate register class descriptors. 
Add a mechanism for defining sub-classes of register classes.
 2017-01-20 14:23:06 -08:00
Jakob Stoklund Olesen
353caf23cd Generate register bank descriptions. 
Use the information in the ISA's registers.py files to generate a
RegInfo Rust data structure.
 2016-11-22 18:15:21 -08:00
Jakob Stoklund Olesen
060735adfe Define register classes for 4 ISAs. 2016-11-11 15:08:12 -08:00
Jakob Stoklund Olesen
e1c0171b2c Define register banks. 
Add a RegBank class for describing CPU register banks.

Define register banks for all the ISA stubs. The ARM32 floating point
bank in particular requires attention.
 2016-11-11 14:17:10 -08:00
Jakob Stoklund Olesen
581294dafe Use uppercase for the global riscv.ISA constant. 2016-11-11 11:17:40 -08:00
Jakob Stoklund Olesen
8846cb8105 Move ISA definitions into cdsl.isa. 
The cretonne package is now split into two: cdsl and base.
 2016-11-08 13:21:05 -08:00
Jakob Stoklund Olesen
0b9b956695 Split out instruction definitions. 
- cdsl.instructions defines the Instruction class.
- base.instructions defines the base instruction set.
 2016-11-08 12:33:50 -08:00
Jakob Stoklund Olesen
eb688dc72d Move formats, entities, and immediates to the base package. 
- base.formats defines instruction formats.
- base.entities defines kinds of entity references.
- base.immediates defines kinds of imediate operands.
 2016-11-08 11:06:37 -08:00
Jakob Stoklund Olesen
e6b959436d Split out predicates and settings. 
- cdsl.predicates defines classes for describing predicates.
- cdsl.settings defines classes for describing settings.
- base.settings defines shared settings.
 2016-11-08 10:37:17 -08:00
Jakob Stoklund Olesen
ed917c394f Add PEP 484 type annotations to a bunch of Python code. 
Along with the mypy tool, this helps find bugs in the Python code
handling the instruction definition data structures.
 2016-10-26 15:15:51 -07:00
Jakob Stoklund Olesen
af6355e2ef Move the 'meta' dir to 'lib/cretonne/meta'. 
The 'lib/cretonne' directory will be the new root of a stand-alone
cretonne crate containg both Python and Rust sources.

This is in preparation for publishing crates on crates.io.
 2016-10-17 14:19:23 -07:00