Jakob Stoklund Olesen
479ff156c1
Add conditional branch encodings for RISC-V.
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Not all br_icmp opcodes are present in the ISA. The missing ones can be
reached by commuting operands.
Don't attempt to encode EBB offsets yet. For now just emit an EBB
relocation for the branch instruction.
2017-04-03 15:16:25 -07:00
Jakob Stoklund Olesen
0530e822d4
Add RISC-V encodings for lui.
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This instruction can materialize constants with the low 12 bits clear.
2017-04-03 12:27:22 -07:00
Jakob Stoklund Olesen
4e398164d2
Add icmp_imm encodings for RISC-V.
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The ISA has icmp_imm slt/ult with 12-bit signed immediate operands.
2017-04-03 10:59:28 -07:00
Jakob Stoklund Olesen
9ddbc5d861
Emit Rshamt-type instructions for RISC-V.
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These are the shift-by-immediate instructions.
2017-03-31 15:33:21 -07:00
Jakob Stoklund Olesen
c9a14448b8
Emit I-type instructions for RISC-V.
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These are the BinaryImm formats.
2017-03-31 15:15:20 -07:00
Jakob Stoklund Olesen
e9907fbdd6
Add RISC-V encodings for supported icmp variants.
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Only slt and ult variants are in the instruction set. Other condition
codes must be synthesized.
2017-03-31 13:47:07 -07:00
Jakob Stoklund Olesen
4613cbcf18
Test binary encodings of some RV32I instructions.
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These are the R-format instructions in RV32I.
2017-03-29 13:16:12 -07:00
Jakob Stoklund Olesen
6ad34f90aa
Allow for unencoded instructions in the binemit tests.
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If an instruction doesn't have an associated encoding, use the standard
TargetIsa hook to encode it.
The test still fails if an instruction can't be encoded. There is no
legalization step.
2017-03-29 09:55:49 -07:00
Jakob Stoklund Olesen
f540cb0664
Add a binemit test command.
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This makes it possible to write file tests that verify the binary
encoding of machine code.
2017-03-28 15:56:30 -07:00
