Commit Graph

7 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
71128611a7 Extract the topological ordering into a module.
Multiple passes will need to iterate over EBBs in a
dominator-topological order. Move that functionality into a separate
module.
2017-04-27 17:39:58 -07:00
Eric Anholt
43ce26e64b Verify that the instruction encoding matches what the ISA would encode.
Fixes #69
2017-04-23 17:21:32 -07:00
Jakob Stoklund Olesen
d0d5f3bb26 Run the post-regalloc verification inside the regalloc context.
This means that we can verify the basics with verify_context before
moving on to verifying the liveness information.

Live ranges are now verified immediately after computing them and after
register allocation is complete.
2017-04-21 16:25:24 -07:00
Jakob Stoklund Olesen
c5da572ebb Add a liveness verifier.
The liveness verifier will check that the live ranges are consistent
with the function. It runs as part of the register allocation pipeline
when enable_verifier is set.

The initial implementation checks the live ranges, but not the
ISA-specific constraints and affinities.
2017-04-21 16:01:08 -07:00
Jakob Stoklund Olesen
1984c96f7c rustfmt 0.8.1 2017-04-05 09:00:11 -07:00
Jakob Stoklund Olesen
a9056f699e Rename the 'cfg' module to 'flowgraph'.
The 'cfg' name was easy to confuse with 'configuration'.
2017-03-21 15:33:23 -07:00
Jakob Stoklund Olesen
bf9cf09622 Add a register allocation context module.
Collect the data structures that hang around between function
compilations.

Provide a main entry point to the register allocator passes.
2017-02-22 11:53:01 -08:00