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39e102b155b192fcfdbcb6515f90545ba90b19dd
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7 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
39e102b155 Add conditional branch encodings for RISC-V. 
Not all br_icmp opcodes are present in the ISA. The missing ones can be
reached by commuting operands.

Don't attempt to encode EBB offsets yet. For now just emit an EBB
relocation for the branch instruction.
 2017-04-03 15:16:25 -07:00
Jakob Stoklund Olesen
175b269760 Add RISC-V encodings for lui. 
This instruction can materialize constants with the low 12 bits clear.
 2017-04-03 12:27:22 -07:00
Jakob Stoklund Olesen
c13c318ec4 Add icmp_imm encodings for RISC-V. 
The ISA has icmp_imm slt/ult with 12-bit signed immediate operands.
 2017-04-03 10:59:28 -07:00
Jakob Stoklund Olesen
39fc0eb3cf Add RISC-V encodings for supported icmp variants. 
Only slt and ult variants are in the instruction set. Other condition
codes must be synthesized.
 2017-03-31 13:47:07 -07:00
Jakob Stoklund Olesen
62334b26b4 Add return_reg encodings for RISC-V. 2017-02-21 16:29:23 -08:00
Jakob Stoklund Olesen
5fa322f797 Split out instruction definitions. 
- cdsl.instructions defines the Instruction class.
- base.instructions defines the base instruction set.
 2016-11-08 12:33:50 -08:00
Jakob Stoklund Olesen
e7f30a40b4 Move the 'meta' dir to 'lib/cretonne/meta'. 
The 'lib/cretonne' directory will be the new root of a stand-alone
cretonne crate containg both Python and Rust sources.

This is in preparation for publishing crates on crates.io.
 2016-10-17 14:19:23 -07:00