Commit Graph

19 Commits

Author SHA1 Message Date
Benjamin Bouvier
350b3b2406 [meta] Avoid unwrapping instructions several times during legalization;
This avoids doing multiple unpacking of the InstructionData for a single
legalization, improving readability and reducing size of the generated
code. For instance, icmp had to unpack the format once per IntCC
condition code.
2019-10-15 11:37:48 +02:00
Andrew Brown
1f728c1797 Add x86 legalization for SIMD bnot 2019-10-11 11:05:24 -07:00
Andrew Brown
6d690e5275 Allow binding immediates to instructions (#1012)
This change should make the code more clear (and less code) when adding encodings for instructions with specific immediates; e.g., a constant with a 0 immediate could be encoded as an XOR with something like `const.bind(...)` without explicitly creating the necessary predicates. It has several parts:
* Introduce Bindable trait to instructions
* Convert all instruction bindings to use Bindable::bind()
* Add ability to bind immediates to BoundInstruction
This is an attempt to reduce some of the issues in #955.
2019-10-10 08:54:46 -07:00
Andrew Brown
ba393afd4d Add x86 legalization for SIMD ineg 2019-09-30 13:54:30 -07:00
Andrew Brown
a3db30d97e Add x86 encoding for SIMD icmp eq
Also adds a predicate for matching the `eq` IntCC code (TODO this should be replaced by something more general)
2019-09-24 09:33:07 -07:00
Andrew Brown
af1499ce99 Add x86 implementation of shuffle 2019-09-19 10:53:40 -07:00
Ujjwal Sharma
3418fb6e18 [codegen] reintroduce support for carry and borrow instructions in RI… (#1005)
Reintroduce support for iadd carry variants and isub borrow variants for
RISC ISAs which had been removed in
https://github.com/CraneStation/cranelift/pull/961 and
https://github.com/CraneStation/cranelift/pull/962 because of the lack
of a proper flags register in RISC architectures.
2019-09-13 17:27:49 +02:00
Andrew Brown
295b2ef614 Avoid extra register movement when lowering an x86 insertlane to a float vector 2019-09-10 10:45:12 -07:00
Andrew Brown
00bedca274 Avoid extra register movement when lowering the x86 extractlane of a float vector
This commit is based on the assumption that floats are already stored in XMM registers in x86. When extracting a lane, cranelift was moving the float to a regular register and back to an XMM register; this change avoids this by shuffling the float value to the lowest bits of the XMM register. It also assumes that the upper bits can be left as is (instead of zeroing them out).
2019-09-10 10:45:12 -07:00
Andrew Brown
ebc783e49b Use raw_bitcast when legalizing splat
raw_bitcast matches the intent of this legalization more clearly (to simply change the CLIF type without changing any bits) and the additional null encodings added are necessary for later instructions
2019-09-10 10:45:12 -07:00
Benjamin Bouvier
d1d2e790b9 [meta] Morph a few pub into pub(crate), and remove dead code; 2019-09-06 15:47:20 +02:00
Benjamin Bouvier
29e3ec51c1 [meta] Introduce the Immediates structure instead of using dynamic lookup; 2019-09-06 15:47:20 +02:00
Andrew Brown
d492cf7e0e Avoid unnecessary lane calculations in codegen code
This refactor moves the calculation of the number of lanes to code closer to where the Instruction/BoundInstruction is bound.
2019-08-20 10:21:12 -07:00
Andrew Brown
084e279def Add x86 implementation of splat instruction 2019-07-16 17:07:44 -07:00
Benjamin Bouvier
70f79d23bf [meta] Make Builders build() instead of finish(); 2019-05-29 14:05:01 +02:00
Benjamin Bouvier
22a6823496 [meta] Rename cdsl/inst to cdsl/instructions; 2019-05-29 14:05:01 +02:00
Benjamin Bouvier
6935033c9e [meta] Have bind() be a method of {Bound,}Instruction instead of a static method; 2019-05-23 14:31:00 +02:00
Benjamin Bouvier
a46b2d7173 [meta] Move ApplyTarget/bind to cdsl/inst; 2019-05-23 14:31:00 +02:00
Benjamin Bouvier
d00e42ede3 [meta] Port shared and x86 legalizations to the Rust crate; 2019-04-25 11:44:56 +02:00