Commit Graph

16 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
315c858b48 Append link and sret arguments in legalize_signature.
These special-purpose arguments and return values are only relevant for
the function being compiled, so add a `current` flag to
legalize_signature().

- Add the necessary argument values to the entry block to represent
  the special-purpose arguments.
- Propagate the link and sret arguments to return instructions if the
  legalized signature asks for it.
2017-04-19 15:55:12 -07:00
Jakob Stoklund Olesen
9c6a36d36d Move the ctrl_typevar function into dfg.
Soon, InstructionData won't have sufficient information to compute this.

Give TargetIsa::encode() an explicit ctrl_typevar argument. This
function does not require the instruction to be inserted in the DFG
tables.
2017-04-12 14:32:13 -07:00
Jakob Stoklund Olesen
eb1052718b Add encoding size information to EncInfo.
Two new pieces of information are available for all encoding recipes:

- The size in bytes of an encoded instruction, and
- The range of a branch encoded with the recipe, if any.

In the meta language, EncRecipe takes two new constructor arguments. The
size is required for all encodings and branch_range is required for all
recipes used to encode branches.
2017-04-05 11:46:19 -07:00
Jakob Stoklund Olesen
6ab35e54b8 Move encoding-related information into an EncInfo struct.
The tables returned by recipe_names() and recipe_constraints() are now
collected into an EncInfo struct that is available from
TargetIsa::encoding_info(). This is equivalent to the register bank
tables available fro TargetIsa::register_info().

This cleans of the TargetIsa interface and makes it easier to add
encoding-related information.
2017-04-05 10:07:19 -07:00
Jakob Stoklund Olesen
39e102b155 Add conditional branch encodings for RISC-V.
Not all br_icmp opcodes are present in the ISA. The missing ones can be
reached by commuting operands.

Don't attempt to encode EBB offsets yet. For now just emit an EBB
relocation for the branch instruction.
2017-04-03 15:16:25 -07:00
Jakob Stoklund Olesen
ca2b1c79d7 Generate binemit::emit_inst() functions.
Use the meta language encoding recipes to generate an emit_inst()
function for each ISA. The generated calls into recipe_*() functions
that must be implemented by hand.

Implement recipe_*() functions for the RISC-V recipes.

Add the TargetIsa::emit_inst() entry point which emits an instruction to
a CodeSink trait object.
2017-03-28 14:44:36 -07:00
Jakob Stoklund Olesen
408395db25 Add a legalize_signature method to TargetIsa.
This entry point will be used for controlling ABI conventions when
legalizing.

Provide an empty implementation for RISC-V and let the other ISAs crash
in legalization.

This is just the scaffolding. We still need to:

- Rewrite the entry block arguments to match the legalized signature.
- Rewrite call and return instructions.
- Implement the legalize_signature() function for all ISAs.
- Add shared generic types to help with the legalize_signature()
  functions.
2017-03-03 11:00:26 -08:00
Jakob Stoklund Olesen
2361467536 Return RegInfo by value from TargetIsa::register_info().
The struct is just a pair of static references, and we don't need the
double indirection.
2017-02-14 16:05:54 -08:00
Jakob Stoklund Olesen
3c4d54c4bd Implement value affinities for register allocation.
An SSA value is usually biased towards a specific register class or a
stack slot, depending on the constraints of the instructions using it.

Represent this bias as an Affinity enum, and implement a merging
algorithm for updating an affinity to satisfy a new constraint.

Affinities will be computed as part of the liveness analysis. This is
not implemented yet.
2017-01-27 10:22:50 -08:00
Jakob Stoklund Olesen
0394f35034 Add operand register constraints.
Every encoding recipe must specify register constraints on input and
output values.

Generate recipe constraint tables along with the other encoding tables.
2017-01-25 13:35:18 -08:00
Jakob Stoklund Olesen
58dedb673a Add an AllocatableSet for registers.
This set of available register units also manages register aliasing in
an efficient way.

Detect if the units in a register straddles mask words. The algorithm
for allocating multi-unit registers expect the whole register to be
inside a single mask word. We could handle this if necessary, but so far
no ISAs need it.
2017-01-23 12:43:32 -08:00
Jakob Stoklund Olesen
19ac05577c Fill in boilerplate for Intel and ARM targets.
The intel, arm32, and arm32 targets were only defined in the meta
language previously. Add Rust implementations too.

This is mostly boilerplate, except for the unit tests in the
registers.rs files.
2016-11-23 10:42:07 -08:00
Jakob Stoklund Olesen
1f6dd0dab7 Generate register bank descriptions.
Use the information in the ISA's registers.py files to generate a
RegInfo Rust data structure.
2016-11-22 18:15:21 -08:00
Jakob Stoklund Olesen
e24291fe4c Return a Result from the TargetIsa::encode() method.
When an instruction can't be encoded, provide a viable legalization
action in the form of a Legalize enum.
2016-11-03 19:15:36 -07:00
Jakob Stoklund Olesen
3da569de06 Require documentation on cretonne public items. 2016-10-26 19:10:06 -07:00
Jakob Stoklund Olesen
0764df28b5 Move library crates under 'lib/'.
Give these crates each a more standard directory layout with sources in
a 'src' sub-sirectory and Cargo.toml in the top lib/foo directory.

Add license and description fields to each.

The build script for the cretonne crate now lives in
'lib/cretonne/build.rs' separating it from the normal library sources
under 'lib/cretonne/src'.
2016-10-17 14:44:43 -07:00