Commit Graph

30 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
8abcdac5a1 Legalize fcvt_to_sint and fcvt_to_uint for Intel64.
We need to generate traps on NaN and overflow.
2017-09-28 12:00:38 -07:00
Jakob Stoklund Olesen
34146435e5 Legalize unsigned-to-float conversions for Intel 64.
Also make sure we generate type checks for the controlling type variable
in legalization patterns. This is not needed for encodings since the
encoding tables are already keyed on the controlling type variable.
2017-09-28 11:39:19 -07:00
Jakob Stoklund Olesen
b6b474a8c9 Add Intel legalization for fmin and fmax.
The native x86_fmin and x86_fmax instructions don't behave correctly for
NaN inputs and when comparing +0.0 to -0.0, so we need separate branches
for those cases.
2017-09-27 12:55:34 -07:00
Jakob Stoklund Olesen
6ff681a90d Add general legalization for the select instruction. 2017-09-26 14:16:35 -07:00
Jakob Stoklund Olesen
7fb6159a85 Add Intel encodings for the fcmp instruction.
Not all floating point condition codes are directly supported by the
ucimiss/ucomisd instructions. Some inequalities need to be reversed and
eq+ne require two separate tests.
2017-09-26 11:17:32 -07:00
Jakob Stoklund Olesen
79968a2325 Add standard expansions for fcopysign.
This is also just a sign bit manipulation.
2017-09-25 15:17:32 -07:00
Jakob Stoklund Olesen
6bec5f8507 Intel encodings for nearest/floor/ceil/trunc.
These floating point rounding operations all use the roundss/roundsd
instructions that are available in SSE 4.1.
2017-09-25 15:08:04 -07:00
Jakob Stoklund Olesen
ac343ba92a Add encodings for square root instructions. 2017-09-25 13:15:09 -07:00
Jakob Stoklund Olesen
8deca67968 Add legalization patterns for fabs and fneg.
These sign bit manipulations need to use a -0.0 floating point constant
which we didn't have a way of materializing previously.

Add a ieee32.bits(0x...) syntax to the Python AST nodes that creates am
f32 immediate value with the exact requested bitwise representation.
2017-09-25 12:15:33 -07:00
Jakob Stoklund Olesen
ba1c50d6c1 Test WebAssembly floating point constants.
f64.const does not yet work on 32-bit Intel.
2017-09-25 11:06:18 -07:00
Jakob Stoklund Olesen
fdb97da21b Implement a poor man's jump table.
We will eventually support real jump tables, but for now just expand
br_table into a sequence of conditional branches.
2017-09-25 10:56:14 -07:00
Jakob Stoklund Olesen
e8723be33f Add trap codes to the Cretonne IL.
The trap and trapz/trapnz instructions now take a trap code immediate
operand which indicates the reason for trapping.
2017-09-20 15:50:02 -07:00
Jakob Stoklund Olesen
1fdeddd0d3 Add Intel encodings for floating point load/store instructions.
Include wasm/*-memory64.cton tests too.
2017-09-19 09:32:54 -07:00
Jakob Stoklund Olesen
54534e2147 Add Intel legalization for division and multiplication.
These operations need custom legalization in order to use Intel's div
and idiv instructions.
2017-07-28 16:41:59 -07:00
Jakob Stoklund Olesen
051aaed43e Add Intel encodings for more conversion instructions.
The following instructions have simple encodings:

- bitcast.f32.i32
- bitcast.i32.f32
- bitcast.f64.i64
- bitcast.i64.f64
- fpromote.f64.f32
- fdemote.f32.f64

Also add helper functions enc_flt() and enc_i32_i64 to
intel.encodings.py for generating the common set of encodings for an
instruction: I32, I64 w/REX, I64 w/o REX.
2017-07-27 11:08:41 -07:00
Jakob Stoklund Olesen
43e190ad20 Intel encodings for fadd, fsub, fmul, fdiv. 2017-07-20 10:40:11 -07:00
Jakob Stoklund Olesen
e3f6755264 Add some signed int to float conversions.
These map to single Intel instructions.

The i64 to float conversions are not tested yet. The encoding tables
can't yet differentiate instructions on a secondary type variable alone.
2017-07-19 15:35:13 -07:00
Jakob Stoklund Olesen
87c5f27ff7 Intel encodings for trap.
Use a ud2 instruction which generates an undefined instruction
exception.
2017-07-19 15:01:32 -07:00
Jakob Stoklund Olesen
b59b348a1e Add Intel encodings for sextend and uextend. 2017-07-19 13:46:49 -07:00
Jakob Stoklund Olesen
9f105145af Add a null encoding for ireduce.i32.i64.
This conversion doesn't require any code, we're just looking at the bits
differently.
2017-07-19 13:11:11 -07:00
Jakob Stoklund Olesen
f03f1e1898 Add tests for WebAssembly i64 operators.
This only works on 64-bit haswell for now. We need more legalization
patterns for 32-bit ISAs.
2017-07-19 12:56:54 -07:00
Jakob Stoklund Olesen
cfcbf44764 Add tests for WebAssembly i32 comparisons.
One function for each comparison operator.
2017-07-19 12:36:36 -07:00
Jakob Stoklund Olesen
c9bbc1e86e Don't require that the fallthrough instruction has an encoding.
A fallthrough jump is actually represented as 0 bytes, so no encoding is
needed.

Also allow for unencoded instructions in the generated emit_inst
implementations. The verifier has stricter rules for when this is
allowed.
2017-07-19 09:30:04 -07:00
Jakob Stoklund Olesen
efdbf0d735 Add Intel encodings for jump and branch instructions.
Just implement jump, brz, and brnz as needed for WebAssembly.
2017-07-19 09:15:19 -07:00
Jakob Stoklund Olesen
cf876e492a Add Intel encodings for imul. 2017-07-18 09:27:36 -07:00
Jakob Stoklund Olesen
9dc92eb8b3 Add Intel BMI1 ctz and clz encodings. 2017-07-14 14:01:02 -07:00
Jakob Stoklund Olesen
5cbcd59cf0 Add some ISA predicates for Intel CPUID features.
Guard the popcnt instruction on the proper CPUID bits.
2017-07-12 16:05:20 -07:00
Jakob Stoklund Olesen
435a15b88d Add Intel encodings for popcnt.
Change the result type for the bit-counting instructions from a fixed i8
to the iB type variable which is the type of the input. This matches the
convention in WebAssembly, and at least Intel's instructions will set a
full register's worth of count result, even if it is always < 64.

Duplicate the Intel 'ur' encoding recipe into 'umr' and 'urm' variants
corresponding to the RM and MR encoding variants. The difference is
which register is encoded as 'reg' and which is 'r/m' in the ModR/M
byte. A 'mov' register copy uses the MR variant, a unary popcnt uses the
RM variant.
2017-07-12 14:17:16 -07:00
Jakob Stoklund Olesen
f57c666d8a Add Intel encodings for shift and rotate instructions. 2017-07-12 13:12:24 -07:00
Jakob Stoklund Olesen
1f52415b17 Add a WebAssembly filetests directory.
Start adding little 'test compile' test cases which check that the full
compilation pipeline works for each WebAssembly instruction.
2017-07-12 12:22:50 -07:00