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114 Commits

Author SHA1 Message Date
Andrew Brown
8d812b24cc Add x86 encoding for vconst 2019-08-26 16:12:06 -07:00
Andrew Brown
684721ca29 Add x86 recipe for vconst 2019-08-26 16:12:06 -07:00
Andrew Brown
407d24c013 Add operand kind and format for unsigned 128-bit immediates 2019-08-26 16:12:06 -07:00
Ujjwal Sharma
ec8f72bf20 Use roundss/roundsd when available for Ceil/Floor/Trunc/Nearest (#931) 
Don't tie the preexisting SIMD ISA predicates to the shared
enable_simd setting but make new ones instead.

Fixes: https://github.com/CraneStation/cranelift/issues/908
 2019-08-26 13:37:27 +02:00
julian-seward1
b8fb52446c Cranelift: implement redundant fill removal on tree-shaped CFG regions. Mozilla bug 1570584. (#906) 2019-08-25 19:37:34 +02:00
Andrew Brown
cc57e84cbd Fix segfault due to b64 encoding (#919) 
* Fix segfault due to b64 encoding

Prior to this patch, bconst.b64 encoded its instruction with a 32-bit immediate that caused improper decoding of the MOV instruction; instead, use a REX prefix and rely on zero-extension of the immediate. Fixes #911.
 2019-08-23 18:04:34 +02:00
Mike Hommey
97996d79ce Sort custom_legalizes for more deterministic generated code 
For better caching.
 2019-08-22 11:44:19 +02:00
Dan Gohman
13f83d8291 Bump version to 0.40.0 2019-08-20 15:32:19 -07:00
Dan Gohman
0d54517d35 Bump version to 0.39.0 2019-08-20 14:26:16 -07:00
Andrew Brown
b4ef90cfcd Remove SSE2 setting for x86 
In talking to @sunfishcode, he preferred to avoid the confusion of more ISA predicates by eliminating SSE2. SSE2 was released with the Pentium 4 in 2000 so it is unlikely that current CPUs would have SIMD enabled and not have this feature. I tried to note the SSE2-specific instructions with comments in the code.
 2019-08-20 10:21:12 -07:00
Andrew Brown
6605f308b3 Fix static analysis warnings 2019-08-20 10:21:12 -07:00
Andrew Brown
d492cf7e0e Avoid unnecessary lane calculations in codegen code 
This refactor moves the calculation of the number of lanes to code closer to where the Instruction/BoundInstruction is bound.
 2019-08-20 10:21:12 -07:00
Andrew Brown
3fdc78174f Add x86 implementation of extractlane instruction 2019-08-20 10:21:12 -07:00
Carmen Kwan
19257f80c1 Add reference types R32 and R64 
-Add resumable_trap, safepoint, isnull, and null instructions
-Add Stackmap struct and StackmapSink trait

Co-authored-by: Mir Ahmed <mirahmed753@gmail.com>
Co-authored-by: Dan Gohman <sunfish@mozilla.com>
 2019-08-16 11:35:16 -07:00
Benjamin Bouvier
2ee35b7ea1 Implement a Windows Baldrdash calling convention; 2019-08-16 14:25:15 +02:00
Benjamin Bouvier
d8d3602257 Adds the libcall_call_conv setting and use it for libcall calls expansion; 2019-08-12 16:12:00 -07:00
Yury Delendik
00b8d019c9 Bump version to 0.38.0 (#894) 2019-08-06 14:41:13 -05:00
David Lattimore
383ce584ae Fix an assertion that wasn't doing what it said 2019-08-05 15:22:10 +02:00
Nicolas B. Pierron
bc1b56f739 Rename data to inst_data in binemit generated code. 2019-08-02 19:34:18 +02:00
Nicolas B. Pierron
3585ee34b0 Uses divert.apply for all instruction within binemit. 2019-08-02 19:34:18 +02:00
Nicolas B. Pierron
ad71715304 Factor out func.dfg[inst] accesses in binemit. 2019-08-02 19:34:18 +02:00
Benjamin Bouvier
627ba24b59 Simplify jump table instructions and add missing conversion; 
This makes non-legalized jump table instructions operate on operands with
pointer-sized types. This means we need to extend smaller types into the
pointer-sized operand, when the two don't match.
 2019-08-02 18:39:39 +02:00
Dan Gohman
16e16c49a7 Bump version to 0.37.0 2019-07-27 04:50:19 -07:00
Dan Gohman
4641fdd302 Bump version to 0.36.0 2019-07-19 16:28:40 -07:00
Andrew Brown
084e279def Add x86 implementation of splat instruction 2019-07-16 17:07:44 -07:00
Andrew Brown
3b36a1d1d8 Add x86 implementation of insertlane instruction 2019-07-16 17:07:44 -07:00
Andrew Brown
683e7c75a3 Add x86-specific shuffle instructions 
This includes both PSHUFD and PSHUFB; these are necessary to legalize future SIMD instructions.
 2019-07-16 17:07:44 -07:00
Andrew Brown
61772e9775 Add raw_bitcast instruction 
Casts bits as a different type of the same width with no change to the data (unlike bitcast)
 2019-07-16 17:07:44 -07:00
Andrew Brown
5f0e5567c1 Add scalar_to_vector instruction 
Moves scalar values in a GPR register to an FPR register
 2019-07-16 17:07:44 -07:00
Andrew Brown
356e6dafe2 Allow CDSL instructions to bind to vector types 2019-07-16 17:07:44 -07:00
Andrew Brown
659725b465 Add x86-specific SIMD settings, e.g. SSE2 
Also, ties SIMD ISA predicates to the shared enable_simd setting
 2019-07-16 17:07:44 -07:00
Andrew Brown
f2c48009e8 Disable SIMD features by default 2019-07-16 17:07:44 -07:00
Andrew Brown
8378297f33 Prepare legalizer codegen for SIMD features 
Contains fixes from @bnjbvr to codegen as a part of https://github.com/bnjbvr/cranelift/pull/2; necessary for SIMD features to work
 2019-07-16 17:07:44 -07:00
Dan Gohman
67dd0b5015 Bump version to 0.35.0 2019-07-12 15:48:19 -07:00
Benjamin Bouvier
bfc1468688 [docs] Don't accidentally generate doc tests; 2019-07-11 11:48:45 +02:00
Benjamin Bouvier
062ed8f6ea [docs] Remove rst annotations in instructions doc comments; 2019-07-11 11:48:45 +02:00
Benjamin Bouvier
d5b80b2803 [meta] Generate full documentation for instructions in InstBuilder; 2019-07-11 11:48:45 +02:00
Benjamin Bouvier
84a6795873 [meta] Riscv: add back stacknull encodings for copy_nop; 2019-07-10 17:51:09 +02:00
Dan Gohman
59f6c81e4f Bump version to 0.34.0 2019-07-09 12:31:58 -07:00
Benjamin Bouvier
41a3d88b37 Fixes #837: Use an u64 comparison instead of a usize comparison in meta; 2019-07-09 18:15:30 +02:00
Benjamin Bouvier
56f6908020 [meta] Legalization: Don't generate a variable for replaced instructions; 
(since they're unused)
 2019-07-09 10:56:50 +02:00
Benjamin Bouvier
cd4c28ad97 [meta] Legalization: Unprefix some module paths to make code neater; 2019-07-09 10:56:50 +02:00
Benjamin Bouvier
15d8b95e72 [meta] Legalization: remove spurious Option wrapping for type variables; 2019-07-09 10:56:50 +02:00
Benjamin Bouvier
f1222dce10 [meta] Legalization: emit typeof type variables for results in all the cases; 2019-07-09 10:56:50 +02:00
Benjamin Bouvier
4fef03f5f8 [meta] Legalization: remove spurious assert; 
This assert was added when porting legalization from Python to Rust and
doesn't hold when we have derived type variables.
 2019-07-09 10:56:50 +02:00
Benjamin Bouvier
88307f693a [meta] Generate the encodings files; 2019-07-05 17:50:17 +02:00
Benjamin Bouvier
f574ab8703 [meta] Generate the binemits files; 
Co-authored-by: Benjamin Bouvier <public@benj.me>
Co-authored-by: bjorn3 <bjorn3@users.noreply.github.com>
 2019-07-05 17:50:17 +02:00
Benjamin Bouvier
fd03677292 [meta] Recipes and encodings descriptions for x86; 2019-07-05 11:38:51 +02:00
Benjamin Bouvier
ca277422bb [meta] Recipes and encodings descriptions for RiscV; 2019-07-05 11:38:51 +02:00
Benjamin Bouvier
21aaf0c89f [meta] Add cdsl facilities for encodings and recipes; 
Co-authored-by: Benjamin Bouvier <public@benj.me>
Co-authored-by: bjorn3 <bjorn3@users.noreply.github.com>
 2019-07-05 11:38:51 +02:00