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29dfcf5dfbf468e3ef3415e840b2666388c90324
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5 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
29dfcf5dfb Add spill/fill encodings for Intel ISAs. 
To begin with, these are catch-all encodings with a SIB byte and a
32-bit displacement, so they can access any stack slot via both the
stack pointer and the frame pointer.

In the future, we will add encodings for 8-bit displacements as well as
EBP-relative references without a SIB byte.
 2017-09-22 16:05:26 -07:00
Angus Holder
b003605132 Adapt intel to be able to correctly choose compressed instruction encodings: create a register class to identify the lower 8 registers, omit unnecessary REX prefixes, and fix the tests 2017-09-22 07:54:26 -07:00
Jakob Stoklund Olesen
1d21422032 Generate register class descriptors. 
Add a mechanism for defining sub-classes of register classes.
 2017-01-20 14:23:06 -08:00
Jakob Stoklund Olesen
060735adfe Define register classes for 4 ISAs. 2016-11-11 15:08:12 -08:00
Jakob Stoklund Olesen
e1c0171b2c Define register banks. 
Add a RegBank class for describing CPU register banks.

Define register banks for all the ISA stubs. The ARM32 floating point
bank in particular requires attention.
 2016-11-11 14:17:10 -08:00