T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
688 Commits 2 Branches 0 Tags
20ca22f6eb41e9f98be59f6b07c9aa625fb24e8d
Commit Graph

16 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
1c890f317d Add RISC-V call instruction encodings. 
Calls are jal with a fixed %x1 link register.
 2017-04-11 10:40:38 -07:00
Jakob Stoklund Olesen
13b0046ed7 Syntax tweak: Omit comma after an initial enum immediate. 
This affects the comparison instructions which now read "icmp ult a, b".
This mimics LLVM's style and makes it simpler to add instruction flags
in the future, such as "load v1" -> "load aligned v1".

These enumerated operands and flags feel like opcode modifiers rather
than value operands, so displaying them differently makes sense.

Value and numeric operands are still comma separated.
 2017-04-10 10:28:37 -07:00
Jakob Stoklund Olesen
d2f575b54a Add jump encodings to RISC-V. 
Fix a bug in gen_encoding.py when dealing with non-polymorphic
instructions where the type variable is None in Python, VOID in Rust.
 2017-04-06 15:17:57 -07:00
Jakob Stoklund Olesen
e5e5b30315 Add a fallthrough instruction. 
Change jumps to fallthroughs in the branch relaxation pass before
computing the EBB offsets.
 2017-04-06 14:22:32 -07:00
Jakob Stoklund Olesen
1440b673fc Use EBB offsets for encoding RISC-V branches. 
Stop emitting EBB relocations. Use the offsets computed by
relax_branches() to encode the correct displacements immediately.
 2017-04-06 12:55:57 -07:00
Jakob Stoklund Olesen
e56482d0fd Fix a bug in the binemit file test. 
Only emit each instruction once, or the offset computations go all
wrong.
 2017-04-06 11:17:46 -07:00
Jakob Stoklund Olesen
3a47b40ff8 Add RISC-V encodings for brz and brnz. 
These branches compare a register to zero. RISC-V implements this with
the %x0 hard-coded zero register.
 2017-04-03 15:20:57 -07:00
Jakob Stoklund Olesen
39e102b155 Add conditional branch encodings for RISC-V. 
Not all br_icmp opcodes are present in the ISA. The missing ones can be
reached by commuting operands.

Don't attempt to encode EBB offsets yet. For now just emit an EBB
relocation for the branch instruction.
 2017-04-03 15:16:25 -07:00
Jakob Stoklund Olesen
175b269760 Add RISC-V encodings for lui. 
This instruction can materialize constants with the low 12 bits clear.
 2017-04-03 12:27:22 -07:00
Jakob Stoklund Olesen
c13c318ec4 Add icmp_imm encodings for RISC-V. 
The ISA has icmp_imm slt/ult with 12-bit signed immediate operands.
 2017-04-03 10:59:28 -07:00
Jakob Stoklund Olesen
8187fd7371 Emit Rshamt-type instructions for RISC-V. 
These are the shift-by-immediate instructions.
 2017-03-31 15:33:21 -07:00
Jakob Stoklund Olesen
7c9d187b6d Emit I-type instructions for RISC-V. 
These are the BinaryImm formats.
 2017-03-31 15:15:20 -07:00
Jakob Stoklund Olesen
39fc0eb3cf Add RISC-V encodings for supported icmp variants. 
Only slt and ult variants are in the instruction set. Other condition
codes must be synthesized.
 2017-03-31 13:47:07 -07:00
Jakob Stoklund Olesen
a5d4839002 Test binary encodings of some RV32I instructions. 
These are the R-format instructions in RV32I.
 2017-03-29 13:16:12 -07:00
Jakob Stoklund Olesen
1d6049b8f8 Allow for unencoded instructions in the binemit tests. 
If an instruction doesn't have an associated encoding, use the standard
TargetIsa hook to encode it.

The test still fails if an instruction can't be encoded. There is no
legalization step.
 2017-03-29 09:55:49 -07:00
Jakob Stoklund Olesen
36eb39a1f8 Add a binemit test command. 
This makes it possible to write file tests that verify the binary
encoding of machine code.
 2017-03-28 15:56:30 -07:00