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1f17e35e9529254040af7508640605f11a5fa9d6
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3 Commits

Author SHA1 Message Date
Andrew Brown
1f17e35e95 Add x86 SIMD immediate shifts 2019-11-15 13:45:25 -08:00
Andrew Brown
f1904bffea Add x86 SIMD sshr and ushr 
Only the shifts with applicable SSE2 instructions are implemented here: PSRL* (for ushr) only has 16-64 bit instructions and PSRA* (for sshr) only has 16-32 bit instructions.
 2019-10-15 15:51:50 -07:00
Andrew Brown
6460fe705f Add x86 SIMD ishl 
Only the shifts with applicable SSE2 instructions (i.e. 16-64 bit width) are implemented here.
 2019-10-15 15:51:50 -07:00